Kaushik Narayanun

According to our database, Kaushik Narayanun authored at least 8 papers between 2016 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

A Scalable & Cost Efficient Next-Gen Scan Architecture: Streaming Scan Test via NVIDIA MATHS.

Kunal Jain Mangilal, Mahmut Yilmaz, Vishal Agarwal, Shantanu Sarangi, Kaushik Narayanun

Proceedings of the IEEE International Test Conference, 2024

2023

NVIDIA MATHS: Mechanism to Access Test-Data Over High-Speed Links.

Mahmut Yilmaz, Pavan Kumar Datla Jagannadha, Kaushik Narayanun, Shantanu Sarangi, Francisco Da Silva, Joe Sarmiento

IEEE Des. Test, August, 2023

2022

NVIDIA MATHS: Mechanism to Access Test-Data over High-Speed Links.

Mahmut Yilmaz, Pavan Kumar Datla Jagannadha, Kaushik Narayanun, Shantanu Sarangi, Francisco Da Silva, Joe Sarmiento, Smbat Tonoyan, Ashwin Chintaluri, Animesh Khare, Milind Sonawane, Ashish Kumar, Anitha Kalva, Alex Hsu, Jayesh Pandey

Proceedings of the 40th IEEE VLSI Test Symposium, 2022

Observation Point Insertion Using Deep Learning.

Bonita Bhaskaran, Sanmitra Banerjee, Kaushik Narayanun, Shao-Chun Hung, Seyed Nima Mozaffari Mojaveri, Mengyun Liu, Gang Chen, Tung-Che Liang

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

2019

An Efficient Supervised Learning Method to Predict Power Supply Noise During At-speed Test.

Seyed Nima Mozaffari, Bonita Bhaskaran, Kaushik Narayanun, Ayub Abdollahian, Vinod Pagalone, Shantanu Sarangi, Jonathon E. Colburn

Proceedings of the IEEE International Test Conference, 2019

2017

Test-cost optimization in a scan-compression architecture using support-vector regression.

Zipeng Li, Jonathon E. Colburn, Vinod Pagalone, Kaushik Narayanun, Krishnendu Chakrabarty

Proceedings of the 35th IEEE VLSI Test Symposium, 2017

2016

A programmable method for low-power scan shift in SoC integrated circuits.

Ran Wang, Bonita Bhaskaran, Karthikeyan Natarajan, Ayub Abdollahian, Kaushik Narayanun, Krishnendu Chakrabarty, Amit Sanghani

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Test method and scheme for low-power validation in modern SOC integrated circuits.

Bonita Bhaskaran, Amit Sanghani, Kaushik Narayanun, Ayub Abdollahian, Amit Laknaur

Proceedings of the 34th IEEE VLSI Test Symposium, 2016