Doyoung Jang

Orcid: 0000-0002-5629-8294

According to our database1, Doyoung Jang authored at least 16 papers between 2013 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Prediction of Atmospheric Duct Conditions from a Clutter Power Spectrum Using Deep Learning.
Remote. Sens., February, 2024

Design of a Shared-Aperture Dual-Loop Antenna Using a Mutual Complementary Shape to Improve an Electromagnetic Transparent Characteristics Between S/X-Band Elements.
IEEE Access, 2024

2021
Design of an On-Glass 5G Monopole Antenna for a Vehicle Window Glass.
IEEE Access, 2021

2020
Device Scaling roadmap and its implications for Logic and Analog platform.
Proceedings of the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2020

2018
Scaling CMOS beyond Si FinFET: an analog/RF perspective.
Proceedings of the 48th European Solid-State Device Research Conference, 2018

2017
Dedicated technology threshold voltage tuning for 6T SRAM beyond N7.
Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017

Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7.
Proceedings of the 47th European Solid-State Device Research Conference, 2017

2016
5nm: Has the time for a device change come?
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

DenTeach: A Device for Fostering Children's Good Tooth-brushing Habits.
Proceedings of the The 15th International Conference on Interaction Design and Children, 2016

2015
Comparison of NBTI aging on adder architectures and ring oscillators in the downscaling technology nodes.
Microprocess. Microsystems, 2015

Lateral NWFET optimization for beyond 7nm nodes.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Impact of fin shape variability on device performance towards 10nm node.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Dimensioning for power and performance under 10nm: The limits of FinFETs scaling.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Holisitic device exploration for 7nm node.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014

2013
STI and eSiGe source/drain epitaxy induced stress modeling in 28 nm technology with replacement gate (RMG) process.
Proceedings of the European Solid-State Device Research Conference, 2013


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