Aaron Thean

Orcid: 0000-0003-2418-6404

According to our database1, Aaron Thean authored at least 50 papers between 2001 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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On csauthors.net:

Bibliography

2023
A Low-Power DNN Accelerator Enabled by a Novel Staircase RRAM Array.
IEEE Trans. Neural Networks Learn. Syst., August, 2023

Overcoming Negative nFET VTH by Defect-Compensated Low-Thermal Budget ITO-IGZO Hetero-Oxide Channel to Achieve Record Mobility and Enhancement-mode Operation.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Quantile Online Learning for Semiconductor Failure Analysis.
Proceedings of the IEEE International Conference on Acoustics, 2023

2022
Significance of activation functions in developing an online classifier for semiconductor defect detection.
Knowl. Based Syst., 2022

A Wafer Scale Hybrid Integration Platform for Co-packaged Photonics using a CMOS based Optical Interposer<sup>TM</sup>.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Sub-10nm Ultra-thin ZnO Channel FET with Record-High 561 µA/µm ION at VDS 1V, High µ-84 cm<sup>2</sup>/V-s and1T-1RRAM Memory Cell Demonstration Memory Implications for Energy-Efficient Deep-Learning Computing.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021
A 70-μW 1.35-mm<sup>2</sup> Wireless Sensor With 32 Channels of Resistive and Capacitive Sensors and Edge-Encoded PWM UWB Transceiver.
IEEE J. Solid State Circuits, 2021

High-Throughput, Area-Efficient, and Variation-Tolerant 3-D In-Memory Compute System for Deep Convolutional Neural Networks.
IEEE Internet Things J., 2021

2020
A Wireless Multi-Channel Capacitive Sensor System for Efficient Glove-Based Gesture Recognition With AI at the Edge.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A $7\times7\times2$ mm<sup>3</sup> 8.6- $\mu$ W 500-kb/s Transmitter With Robust Injection-Locking-Based Frequency-to-Amplitude Conversion Receiver Targeting for Implantable Applications.
IEEE J. Solid State Circuits, 2020

An 8.2- $\mu$ W 0.14-mm<sup>2</sup> 16-Channel CDMA-Like Capacitance-to-Digital Converter.
IEEE J. Solid State Circuits, 2020

23.2 A 70µW 1.19mm<sup>2</sup> Wireless Sensor with 32 Channels of Resistive and Capacitive Sensors and Edge-Encoded PWM UWB Transceiver.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

Seal Integrity Testing Utilizing Non-Destructive Capacitive Sensing for Product Packaging Assurance.
Proceedings of the 2020 IEEE Sensors, Rotterdam, The Netherlands, October 25-28, 2020, 2020

Quantifying the Benefits of Monolithic 3D Computing Systems Enabled by TFT and RRAM.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Fledge: Flexible Edge Platforms Enabled by In-memory Computing.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Design of Artificial Spiking Neuron with SiO2 Memristive Synapse to Demonstrate Neuron-Level Spike Timing Dependent Plasticity.
Proceedings of the International Conference on IC Design and Technology, 2019

A 7×7×2mm<sup>3</sup> 8.6-μ 500-kb/s Transmitter with Robust Injection-Locking Based Frequency-to-Amplitude Conversion Receiver Targeting for Implantable Applications.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2017
Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and Beyond.
IEEE Trans. Very Large Scale Integr. Syst., 2017

2016
5nm: Has the time for a device change come?
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Physical Design Solutions to Tackle FEOL/BEOL Degradation in Gate-level Monolithic 3D ICs.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016


Non-uniform strain in lattice-mismatched heterostructure tunnel field-effect transistors.
Proceedings of the 46th European Solid-State Device Research Conference, 2016


Effect of material parameters on two-dimensional materials based TFETs: An energy-delay perspective.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

2015

The relationship between border traps characterized by AC admittance and BTI in III-V MOS devices.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Origins and implications of increased channel hot carrier variability in nFinFETs.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

NBTI in Si0.55Ge0.45 cladding p-FinFETs: Porting the superior reliability from planar to 3D architectures.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Area and routing efficiency of SWD circuits compared to advanced CMOS.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Lateral NWFET optimization for beyond 7nm nodes.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Impact of fin shape variability on device performance towards 10nm node.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Assessment of SiGe quantum well transistors for DRAM peripheral applications.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

I/O thick oxide device integration using Diffusion and Gate Replacement (D&GR) gate stack integration.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Nonparabolicity and confinement effects of IIIV materials in novel transistors.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Modeling FinFET metal gate stack resistance for 14nm node and beyond.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Impact of device and interconnect process variability on clock distribution.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

FinFET stressor efficiency on alternative wafer and channel orientations for the 14 nm node and below.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Dimensioning for power and performance under 10nm: The limits of FinFETs scaling.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Characterization and simulation methodology for time-dependent variability in advanced technologies.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

Holisitic device exploration for 7nm node.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

A digital intensive circuit for low-frequency noise monitoring in 28nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014
Determination of energy and spatial distribution of oxide border traps in In<sub>0.53</sub>Ga<sub>0.47</sub>As MOS capacitors from capacitance-voltage characteristics measured at various temperatures.
Microelectron. Reliab., 2014

System-level assessment and area evaluation of Spin Wave logic circuits.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies.
Proceedings of the 44th European Solid State Device Research Conference, 2014


2013
Impact of Al2O3 position on performances and reliability in high-k metal gated DRAM periphery transistors.
Proceedings of the European Solid-State Device Research Conference, 2013

2012
Low-frequency noise assessment of the transport mechanisms in SiGe channel bulk FinFETs.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012

Low-power DRAM-compatible Replacement Gate High-k/Metal Gate stacks.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012

2001
Computer Modeling of Silicon Quantum Dot Floating -Gate Flash Memory Devices
PhD thesis, 2001


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