Bharan Giridhar

According to our database1, Bharan Giridhar authored at least 12 papers between 2011 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2014
13.7 A reconfigurable sense amplifier with auto-zero calibration and pre-amplification in 28nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Integrated 3D-stacked server designs for increasing physical density of key-value stores.
Proceedings of the Architectural Support for Programming Languages and Operating Systems, 2014

2013
Centip3De: A 64-Core, 3D Stacked Near-Threshold System.
IEEE Micro, 2013

A Sub-nW Multi-stage Temperature Compensated Timer for Ultra-Low-Power Sensor Nodes.
IEEE J. Solid State Circuits, 2013

Centip3De: A Cluster-Based NTC Architecture With 64 ARM Cortex-M3 Cores in 3D Stacked 130 nm CMOS.
IEEE J. Solid State Circuits, 2013

Centip3De: a many-core prototype exploring 3D integration and near-threshold computing.
Commun. ACM, 2013

Exploring DRAM organizations for energy-efficient and resilient exascale memories.
Proceedings of the International Conference for High Performance Computing, 2013

A fully integrated successive-approximation switched-capacitor DC-DC converter with 31mV output voltage resolution.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Scaling towards kilo-core processors with asymmetric high-radix topologies.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

Pulse amplification based dynamic synchronizers with metastability measurement using capacitance de-rating.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
Centip3De: A 3930DMIPS/W configurable near-threshold 3D stacked system with 64 ARM Cortex-M3 cores.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011
A 660pW multi-stage temperature-compensated timer for ultra-low-power wireless sensor node synchronization.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011


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