David Fick

According to our database1, David Fick authored at least 29 papers between 2009 and 2020.

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Bibliography

2020

2019
Introduction to Compute-in-Memory.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2017
Low-Power and Compact Analog-to-Digital Converter Using Spintronic Racetrack Memory Devices.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Analog in-memory subthreshold deep neural network accelerator.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016
24.3 A 36.8 2b-TOPS/W self-calibrating GPS accelerator implemented using analog calculation in 65nm LP CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
Racetrack converter: A low power and compact data converter using racetrack spintronic devices.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
Razor-Lite: A Light-Weight Register for Error Detection by Observing Virtual Supply Rails.
IEEE J. Solid State Circuits, 2014

A 346 µm 2 VCO-Based, Reference-Free, Self-Timed Sensor Interface for Cubic-Millimeter Sensor Nodes in 28 nm CMOS.
IEEE J. Solid State Circuits, 2014

16.3 A 23Mb/s 23pJ/b fully synthesized true-random-number generator in 28nm and 65nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Mixed-signal stochastic computation demonstrated in an image sensor with integrated 2D edge detection and noise filtering.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
Circuits for a Cubic-Millimeter Energy-Autonomous Wireless Intraocular Pressure Monitor.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Limits of Parallelism and Boosting in Dim Silicon.
IEEE Micro, 2013

Centip3De: A 64-Core, 3D Stacked Near-Threshold System.
IEEE Micro, 2013

A Millimeter-Scale Energy-Autonomous Sensor System With Stacked Battery and Solar Cells.
IEEE J. Solid State Circuits, 2013

Bubble Razor: Eliminating Timing Margins in an ARM Cortex-M3 Processor in 45 nm CMOS Using Architecturally Independent Error Detection and Correction.
IEEE J. Solid State Circuits, 2013

Centip3De: A Cluster-Based NTC Architecture With 64 ARM Cortex-M3 Cores in 3D Stacked 130 nm CMOS.
IEEE J. Solid State Circuits, 2013

Centip3De: a many-core prototype exploring 3D integration and near-threshold computing.
Commun. ACM, 2013

Razor-lite: A side-channel error-detection register for timing-margin recovery in 45nm SOI CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Pulse amplification based dynamic synchronizers with metastability measurement using capacitance de-rating.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
A Reliable Routing Architecture and Algorithm for NoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Bubble Razor: An architecture-independent approach to timing-error detection and correction.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Centip3De: A 3930DMIPS/W configurable near-threshold 3D stacked system with 64 ARM Cortex-M3 cores.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Assessing the performance limits of parallelized near-threshold computing.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
A cubic-millimeter energy-autonomous wireless intraocular pressure monitor.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
In situ delay-slack monitor for high-performance processors using an all-digital self-calibrating 5ps resolution time-to-digital converter.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Millimeter-scale nearly perpetual sensor system with stacked battery and solar cells.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
Reconfigurable Multicore Server Processors for Low Power Operation.
Proceedings of the Embedded Computer Systems: Architectures, 2009

A highly resilient routing algorithm for fault-tolerant NoCs.
Proceedings of the Design, Automation and Test in Europe, 2009

Vicis: a reliable network for unreliable silicon.
Proceedings of the 46th Design Automation Conference, 2009


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