Yen-Po Chen

According to our database1, Yen-Po Chen authored at least 14 papers between 2012 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2017
11.2 A 1Mb embedded NOR flash memory with 39µW program power for mm-scale high-temperature sensor nodes.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

14.7 A 288µW programmable deep-learning processor with 270KB on-chip weight storage using non-uniform memory hierarchy for mobile intelligence.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2015
An Injectable 64 nW ECG Mixed-Signal SoC in 65 nm for Arrhythmia Monitoring.
IEEE J. Solid State Circuits, 2015

FOCUS: Key building blocks and integration strategy of a miniaturized wireless sensor node.
Proceedings of the ESSCIRC Conference 2015, 2015

2014
Razor-Lite: A Light-Weight Register for Error Detection by Observing Virtual Supply Rails.
IEEE J. Solid State Circuits, 2014

A 266nW multi-chopper amplifier with 1.38 noise efficiency factor for neural signal recording.
Proceedings of the Symposium on VLSI Circuits, 2014

24.3 An implantable 64nW ECG-monitoring mixed-signal SoC for arrhythmia diagnosis.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Circuit techniques for miniaturized biomedical sensors.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
Architecting an LTE base station with graphics processing units.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

Razor-lite: A side-channel error-detection register for timing-margin recovery in 45nm SOI CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Parallelization techniques for implementing trellis algorithms on graphics processors.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

45pW ESD clamp circuit for ultra-low power applications.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
A 2.98nW bandgap voltage reference using a self-tuning low leakage sample and hold.
Proceedings of the Symposium on VLSI Circuits, 2012

A 4.5Tb/s 3.4Tb/s/W 64×64 switch fabric with self-updating least-recently-granted priority and quality-of-service arbitration in 45nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012


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