Iuliana P. Radu

Affiliations:
  • Inter-University Micro-Electronics Center (Imec), Leuven, Belgium


According to our database1, Iuliana P. Radu authored at least 19 papers between 2014 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2021
Solid state qubits: how learning from CMOS fabrication can speed-up progress in Quantum Computing.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

Circuit Model for the Efficient Co-Simulation of Spin Qubits and their Control & Readout Circuitry.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021

Circuit Model for the Efficient Co-Simulation of Spin Qubits and their Control & Readout Circuitry.
Proceedings of the 47th ESSCIRC 2021, 2021

On MX2-based metal-oxide-semiconductor device capacitance-voltage characteristics and dual-gate operation.
Proceedings of the Device Research Conference, 2021

Circuit models for the co-simulation of superconducting quantum computing systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
Quantum Mechanical Charge Trap Modeling to Explain BTI at Cryogenic Temperatures.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Reliability and Variability of Advanced CMOS Devices at Cryogenic Temperatures.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

2019
Reconfigurable nanoscale spin wave majority gate with frequency-division multiplexing.
CoRR, 2019

Tunnel FETs using Phosphorene/ReS2 heterostructures.
Proceedings of the Device Research Conference, 2019

2018
Doping-free complementary inverter enabled by 2D WSe2 electrostatically-doped reconfigurable transistors.
Proceedings of the 76th Device Research Conference, 2018

Spin-based majority gates for logic applications.
Proceedings of the 76th Device Research Conference, 2018

Towards high-performance polarity-controllable FETs with 2D materials.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
WS2 transistors on 300 mm wafers with BEOL compatibility.
Proceedings of the 47th European Solid-State Device Research Conference, 2017

Tunneling transistors based on MoS2/MoTe2 Van der Waals heterostructures.
Proceedings of the 47th European Solid-State Device Research Conference, 2017

Material selection and device design guidelines for two-dimensional materials based TFETs.
Proceedings of the 47th European Solid-State Device Research Conference, 2017

2016
Non-volatile spin wave majority gate at the nanoscale.
CoRR, 2016

Effect of material parameters on two-dimensional materials based TFETs: An energy-delay perspective.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

2015
Area and routing efficiency of SWD circuits compared to advanced CMOS.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

2014
System-level assessment and area evaluation of Spin Wave logic circuits.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014


  Loading...