Iuliana P. Radu

According to our database, Iuliana P. Radu authored at least 30 papers between 2014 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

On the Extreme Scaling of Transistors with Monolayer MOS2 Channel.

Wen-Chia Wu, Terry Y. T. Hung, D. Mahaveer Sathaiya, Edward Chen, Chen-Feng Hsu, Walker Yun, Hsiang-Chi Hu, Bo-Heng Liu, T. Y. Lee, Chi-Chung Kei, Wen-Hao Chang, Jin Cai, W. Jeff, Chung-Cheng Wu, H.-S. Philip Wong, Chao-Hsin Chien, Chao-Ching Cheng, Iuliana P. Radu

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

High Performance Transistor of Aligned Carbon Nanotubes in a Nanosheet Structure.

Nathaniel Safron, Tzu-Ang Chao, Shengman Li, Shreyam Natani, San Lin Liew, Carlo Gilardi, Hsin-Yuan Chiu, Sheng-Kai Su, Andrew Bechdolt, Gilad Zeevi, Zichen Zhang, Matthias Passlack, Vincent D.-H. Hou, Harshil Kashyap, Chao-Hsin Chien, Prabhakar Bandaru, Andrew C. Kummel, H.-S. Philip Wong, Subhasish Mitra, Gregory Pitner, Iuliana P. Radu

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2023

Scaled contact length with low contact resistance in monolayer 2D channel transistors.

Wen-Chia Wu, Terry Y. T. Hung, D. Mahaveer Sathaiya, Dongxu Fan, Goutham Arutchelvan, Chen-Feng Hsu, Sheng-Kai Su, Ang-Sheng Chou, Edward Chen, Weisheng Li, Zhihao Yu, Hao Qiu, Ying-Mei Yang, Kuang-I Lin, Yun-Yang Shen, Wen-Hao Chang, San Lin Liew, Vincent D.-H. Hou, Jin Cai, Chung-Cheng Wu, Jeff Wu, H.-S. Philip Wong, Xinran Wang, Chao-Hsin Chien, Chao-Ching Cheng, Iuliana P. Radu

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Building high performance transistors on carbon nanotube channel.

Gregory Pitner, Nathaniel Safron, Tzu-Ang Chao, Shengman Li, Sheng-Kai Su, Gilad Zeevi, Qing Lin, Hsin-Yuan Chiu, Matthias Passlack, Zichen Zhang, D. Mahaveer Sathaiya, Aslan Wei, Carlo Gilardi, Edward Chen, San Lin Liew, Vincent D.-H. Hou, Chung-Wei Wu, Jeff Wu, Zhiwei Lin, Jeffrey Fagan, Ming Zheng, Han Wang, Subhasish Mitra, H.-S. Philip Wong, Iuliana P. Radu

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Comprehensive 300 mm process for Silicon spin qubits with modular integration.

A. Elsayed, Clement Godfrin, Nard I. Dumoulin Stuyck, M. M. K. Shehata, Stefan Kubicek, S. Massar, Yann Canvel, Julien Jussot, Andriy Hikavyy, Roger Loo, George Simion, Massimo Mongillo, D. Wan, Bogdan Govoreanu, Ruoyu Li, Iuliana P. Radu, Pol Van Dorpe, Kristiaan De Greve

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

How Fault-Tolerant Quantum Computing Benefits from Cryo-CMOS Technology.

H.-L. Chiang, Richard A. Hadi, J.-F. Wang, H.-C. Han, J.-J. Wu, H.-H. Hsieh, J.-J. Horng, W.-S. Chou, B.-S. Lien, C.-H. Chang, Y.-C. Chen, Yeong-Her Wang, T.-C. Chen, J.-C. Liu, Y.-C. Liu, Meng-Hsueh Chiang, K.-H. Kao, B. Pulicherla, J. Cai, C.-S. Chang, K.-W. Su, K.-L. Cheng, T.-J. Yeh, Y.-C. Peng, C. Enz, Mau-Chung Frank Chang, M.-F. Chang, H.-S. Philip Wong, Iuliana P. Radu

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization.

W.-C. Lin, H.-P. Huang, Kuo-Hsing Kao, Meng-Hsueh Chiang, Darsen D. Lu, Wei-Chou Hsu, Yeong-Her Wang, William Cheng-Yu Ma, Hann-Huei Tsai, Y.-J. Lee, H.-L. Chiang, J.-F. Wang, Iuliana P. Radu

Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023

2022

Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections.

A. Vandooren, N. Parihar, Jacopo Franco, Roger Loo, Hiroaki Arimura, R. Rodriguez, F. Sebaai, S. Iacovo, Kevin Vandersmissen, W. Li, G. Mannaert, D. Radisic, E. Rosseel, Andriy Hikavyy, Anne Jourdain, O. Mourey, G. Gaudin, Shay Reboh, L. Le Van-Jodin, Guillaume Besnard, C. Roda Neve, Bich-Yen Nguyen, Iuliana P. Radu, E. Dentoni Litta, N. Horiguchi

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Perspective on Low-dimensional Channel Materials for Extremely Scaled CMOS.

Sheng-Kai Su, Edward Chen, Terry Y. T. Hung, Meng-Zhan Li, Gregory Pitner, Chao-Ching Cheng, Han Wang, Jin Cai, H.-S. Philip Wong, Iuliana P. Radu

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Wafer-Scale Bi-Assisted Semi-Auto Dry Transfer and Fabrication of High-Performance Monolayer CVD WS2 Transistor.

Ming-Yang Li, Ching-Hao Hsu, Shin-Wei Shen, Ang-Sheng Chou, Yuxuan Cosmi Lin, Chih-Piao Chuu, Ning Yang, Sui-An Chou, Lin-Yun Huang, Chao-Ching Cheng, Wei-Yen Woon, Szuya Liao, Chih-I Wu, Lain-Jong Li, Iuliana P. Radu, H.-S. Philip Wong, Han Wang

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Scalable 1.4 μW cryo-CMOS SP4T multiplexer operating at 10 mK for high-fidelity superconducting qubit measurements.

Rohith Acharya, Anton Potocnik, Steven Brebels, Alexander Grill, Jeroen Verjauw, Tsvetan Ivanov, Daniel Perez Lozano, Danny Wan, Fahd A. Mohiyaddin, Jacques Van Damme, A. M. Vadiraj, Massimo Mongillo, Georges G. E. Gielen, Francky Catthoor, Jan Craninckx, Iuliana P. Radu, Bogdan Govoreanu

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021

Uniform Spin Qubit Devices with Tunable Coupling in an All-Silicon 300 mm Integrated Process.

Nard I. Dumoulin Stuyck, Roy Li, Clement Godfrin, Asser Elsayed, Stefan Kubicek, Julien Jussot, B. T. Chan, Fahd A. Mohiyaddin, Mohamed Shehata, George Simion, Yann Canvel, Ludovic Goux, Heyns Heyns, Bogdan Govoreanu, Iuliana P. Radu

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

Solid state qubits: how learning from CMOS fabrication can speed-up progress in Quantum Computing.

Iuliana P. Radu, Roy Li, Anton Potocnik, Tsvetan Ivanov, Danny Wan, Stefan Kubicek, Nard I. Dumoulin Stuyck, Jeroen Verjauw, Julien Jussot, Yann Canvel, Clement Godfrin, Massimo Mongillo, Rohith Acharya, Asser Elsayed, Mohamed Shehata, Xiaoyu Piao, Antoine Pacco, Laurent Souriau, Sebastien Couet, B. T. Chan, Jan Craninckx, Bertrand Parvais, Alexander Grill, Subramanian Narasimhamoorthy, Steven Van Winckel, Steven Brebels, Fahd A. Mohiyaddin, George Simion, Bogdan Govoreanu

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

Circuit Model for the Efficient Co-Simulation of Spin Qubits and their Control & Readout Circuitry.

Benjamin Gys, Fahd A. Mohiyaddin, Rohith Acharya, Roy Li, Kristiaan De Greve, Georges G. E. Gielen, Bogdan Govoreanu, Iuliana P. Radu, Francky Catthoor

Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021

On MX2-based metal-oxide-semiconductor device capacitance-voltage characteristics and dual-gate operation.

Dennis Lin, Xiangyu Wu, Vivek Mootheri, Daire Cott, Benjamin Groven, Pierre Morin, Inge Asselberghs, Iuliana P. Radu

Proceedings of the Device Research Conference, 2021

Circuit models for the co-simulation of superconducting quantum computing systems.

Rohith Acharya, Fahd A. Mohiyaddin, Anton Potocnik, Kristiaan De Greve, Bogdan Govoreanu, Iuliana P. Radu, Georges G. E. Gielen, Francky Catthoor

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Quantum Mechanical Charge Trap Modeling to Explain BTI at Cryogenic Temperatures.

Jakob Michl, Alexander Grill, Dieter Claes, Gerhard Rzepa, Ben Kaczer, Dimitri Linten, Iuliana P. Radu, Tibor Grasser, Michael Waltl

Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Reliability and Variability of Advanced CMOS Devices at Cryogenic Temperatures.

Alexander Grill, Erik Bury, Jakob Michl, Stanislav Tyaginov, Dimitri Linten, Tibor Grasser, Bertrand Parvais, Ben Kaczer, Michael Waltl, Iuliana P. Radu

Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

2019

Reconfigurable nanoscale spin wave majority gate with frequency-division multiplexing.

Giacomo Talmelli, Thibaut Devolder, Nick Träger, Johannes Förster, Sebastian Wintz, Markus Weigand, Hermann Stoll, Marc M. Heyns, Gisela Schütz, Iuliana P. Radu, Joachim Gräfe, Florin Ciubotaru, Christoph Adelmann

CoRR, 2019

Tunnel FETs using Phosphorene/ReS2 heterostructures.

Yashwanth Balaji, Quentin Smets, Dennis Lin, I. Asselberghs, Iuliana P. Radu, Guido Groeseneken

Proceedings of the Device Research Conference, 2019

2018

Doping-free complementary inverter enabled by 2D WSe2 electrostatically-doped reconfigurable transistors.

Giovanni V. Resta, Yashwanth Balaji, Dennis Lin, Iuliana P. Radu, Francky Catthoor, Pierre-Emmanuel Gaillardon, Giovanni De Micheli

Proceedings of the 76th Device Research Conference, 2018

Spin-based majority gates for logic applications.

Iuliana P. Radu

Proceedings of the 76th Device Research Conference, 2018

Towards high-performance polarity-controllable FETs with 2D materials.

Giovanni V. Resta, Jorge Romero Gonzalez, Yashwanth Balaji, Tarun Agarwal, Dennis Lin, Francky Catthoor, Iuliana P. Radu, Giovanni De Micheli, Pierre-Emmanuel Gaillardon

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

WS2 transistors on 300 mm wafers with BEOL compatibility.

Tom Schram, Quentin Smets, Benjamin Groven, M. H. Heyne, E. Kunnen, A. Thiam, Katia Devriendt, Annelies Delabie, Dennis Lin, M. Lux, Daniele Chiappe, I. Asselberghs, S. Brus, Cedric Huyghebaert, S. Sayan, A. Juncker, Matty Caymax, Iuliana P. Radu

Proceedings of the 47th European Solid-State Device Research Conference, 2017

Tunneling transistors based on MoS2/MoTe2 Van der Waals heterostructures.

Yashwanth Balaji, Quentin Smets, Cesar J. Lockhart de la Rosa, Anh Khoa Augustin Lu, Daniele Chiappe, Tarun Agarwal, Dennis Lin, Cedric Huyghebaert, Iuliana P. Radu, Dan Mocuta, Guido Groeseneken

Proceedings of the 47th European Solid-State Device Research Conference, 2017

Material selection and device design guidelines for two-dimensional materials based TFETs.

Tarun Agarwal, Bart Soree, Iuliana P. Radu, Praveen Raghavan, Gianluca Fiori, Marc M. Heyns, Wim Dehaene

Proceedings of the 47th European Solid-State Device Research Conference, 2017

2016

Non-volatile spin wave majority gate at the nanoscale.

Odysseas Zografos, Sourav Dutta, Mauricio Manfrini, Adrien Vaysset, Bart Sorée, Azad Naeemi, Praveen Raghavan, Rudy Lauwereins, Iuliana P. Radu

CoRR, 2016

Effect of material parameters on two-dimensional materials based TFETs: An energy-delay perspective.

Tarun Agarwal, Iuliana P. Radu, Praveen Raghavan, Gianluca Fiori, Aaron Thean, Marc M. Heyns, Wim Dehaene

Proceedings of the ESSCIRC Conference 2016: 42^nd European Solid-State Circuits Conference, 2016

2015

Area and routing efficiency of SWD circuits compared to advanced CMOS.

Odysseas Zografos, Praveen Raghavan, Yasser Sherazi, Adrien Vaysset, Florin Ciubotaru, Bart Soree, Rudy Lauwereins, Iuliana P. Radu, Aaron Thean

Proceedings of the 2015 International Conference on IC Design & Technology, 2015

2014

System-level assessment and area evaluation of Spin Wave logic circuits.

Odysseas Zografos, Praveen Raghavan, Luca Gaetano Amarù, Bart Soree, Rudy Lauwereins, Iuliana P. Radu, Diederik Verkest, Aaron Thean

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014