Dominik Germek

Orcid: 0000-0003-3812-727X

According to our database1, Dominik Germek authored at least 44 papers between 2014 and 2025.

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Bibliography

2025
It's Getting Hot in Here: Hardware Security Implications of Thermal Crosstalk on ReRAMs.
IEEE Trans. Reliab., December, 2025

OptiLock: Automated Optimization of Learning-Resilient Logic Locking.
IEEE Access, 2025

ALDExA: Automated LLM-Assisted Detection of CVE Exploitation Attempts in Host-Captured Data.
IEEE Access, 2025

Beekeeper: Accelerating Honeypot Analysis With LLM-Driven Feedback.
IEEE Access, 2025

The Impact of Logic Locking on Confidentiality: An Automated Evaluation.
Proceedings of the 26th International Symposium on Quality Electronic Design, 2025

2024
Exploiting the Lock: Leveraging MiG-V's Logic Locking for Secret-Data Extraction.
CoRR, 2024

QTFlow: Quantitative Timing-Sensitive Information Flow for Security-Aware Hardware Design on RTL.
CoRR, 2024

Work-in-Progress: Emerging E/E-Architectures as Enabler for Automotive Honeypots.
Proceedings of the IEEE European Symposium on Security and Privacy Workshops, 2024

NVM-Flip: Non-Volatile-Memory BitFlips on the System Level.
Proceedings of the 2024 ACM Workshop on Secure and Trustworthy Cyber-Physical Systems, 2024

2023
A survey of contemporary open-source honeypots, frameworks, and tools.
J. Netw. Comput. Appl., November, 2023

SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors.
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023

Enhancing HW-SW Confidentiality Verification for Embedded Processors with SoftFlow's Advanced Memory Range Feature.
Proceedings of the VLSI-SoC 2023: Innovations for Trustworthy Artificial Intelligence, 2023

Gate Camouflaging Using Reconfigurable ISFET-Based Threshold Voltage Defined Logic.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

Invited Paper: A Holistic Fault Injection Platform for Neuromorphic Hardware.
Proceedings of the 24th IEEE Latin American Test Symposium, 2023

Quantitative Information Flow for Hardware: Advancing the Attack Landscape.
Proceedings of the 14th IEEE Latin America Symposium on Circuits and System, 2023

DeepAttack: A Deep Learning Based Oracle-less Attack on Logic Locking.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

AutoLock: Automatic Design of Logic Locking with Evolutionary Computation.
Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2023

Fault Injection in Native Logic-in-Memory Computation on Neuromorphic Hardware.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Work-in-Progress: A Universal Instrumentation Platform for Non-Volatile Memories.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2023

2022
Designing trustworthy hardware with logic locking.
PhD thesis, 2022

Deceptive Logic Locking for Hardware Integrity Protection Against Machine Learning Attacks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

A Temperature Independent Readout Circuit for ISFET-Based Sensor Applications.
Proceedings of the 23rd IEEE Latin American Test Symposium, 2022

pHGen: A pH-Based Key Generation Mechanism Using ISFETs.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022

NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Designing ML-resilient locking at register-transfer level.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

X-Fault: Impact of Faults on Binary Neural Networks in Memristor-Crossbar Arrays with Logic-in-Memory Computation.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021
Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach.
ACM J. Emerg. Technol. Comput. Syst., 2021

ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework.
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities.
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021

Trustworthy Hardware Design with Logic Locking.
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021

QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021

Vertical IP Protection of the Next-Generation Devices: Quo Vadis?
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
A secure hardware-software solution based on RISC-V, logic locking and microkernel.
Proceedings of the SCOPES '20: 23rd International Workshop on Software and Compilers for Embedded Systems, 2020

Scaling Logic Locking Schemes to Multi-module Hardware Designs.
Proceedings of the Architecture of Computing Systems - ARCS 2020, 2020

2019
A Critical Evaluation of the Paradigm Shift in the Design of Logic Encryption Algorithms.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019

Protecting the Integrity of Processor Cores with Logic Encryption.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

Control-Lock: Securing Processor Cores Against Software-Controlled Hardware Trojans.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Inter-Lock: Logic Encryption for Processor Cores Beyond Module Boundaries.
Proceedings of the 24th IEEE European Test Symposium, 2019

2018
Evolving priority rules for resource constrained project scheduling problem with genetic programming.
Future Gener. Comput. Syst., 2018

A Unifying logic encryption security metric.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

2017
Immunological algorithms paradigm for construction of Boolean functions with good cryptographic properties.
Eng. Appl. Artif. Intell., 2017

2016
Evolving Cryptographic Pseudorandom Number Generators.
Proceedings of the Parallel Problem Solving from Nature - PPSN XIV, 2016

Extreme Pipelining Towards the Best Area-Performance Trade-Off in Hardware.
Proceedings of the Progress in Cryptology - AFRICACRYPT 2016, 2016

2014
S-box Pipelining Using Genetic Algorithms for High-Throughput AES Implementations: How Fast Can We Go?
Proceedings of the Progress in Cryptology - INDOCRYPT 2014, 2014


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