Jan Moritz Joseph
Orcid: 0000-0001-8669-1225
According to our database1,
Jan Moritz Joseph
authored at least 46 papers
between 2014 and 2024.
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Bibliography
2024
CoRR, 2024
2023
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2023
Proceedings of the 24th IEEE Latin American Test Symposium, 2023
Proceedings of the 41st IEEE International Conference on Computer Design, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2023
2022
Ratatoskr: An Open-Source Framework for In-Depth Power, Performance, and Area Analysis and Optimization in 3D NoCs.
ACM Trans. Model. Comput. Simul., 2022
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
X-Fault: Impact of Faults on Binary Neural Networks in Memristor-Crossbar Arrays with Logic-in-Memory Computation.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
NEWROMAP: mapping CNNs to NoC-interconnected self-contained data-flow accelerators for edge-AI.
Proceedings of the NOCS '21: International Symposium on Networks-on-Chip, 2021
Technology-aware Router Architectures for On-Chip-Networks in Heterogeneous Technologies.
Proceedings of the NANOCOM '21: The Eighth Annual ACM International Conference on Nanoscale Computing and Communication, Virtual Event, Italy, September 7, 2021
Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021
Bridging the Frequency Gap in Heterogeneous 3D SoCs through Technology-Specific NoC Router Architectures.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
A Systematic Methodology for Characterizing Scalability of DNN Accelerators using SCALE-Sim.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2020
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2020
2019
Simulation environment for link energy estimation in networks-on-chip with virtual channels.
Integr., 2019
Crosstalk optimization for through-silicon vias by exploiting temporal signal misalignment.
Integr., 2019
Ratatoskr: An open-source framework for in-depth power, performance and area analysis in 3D NoCs.
CoRR, 2019
NoCs in Heterogeneous 3D SoCs: Co-Design of Routing Strategies and Microarchitectures.
IEEE Access, 2019
Proceedings of the 8th International Conference on Modern Circuits and Systems Technologies, 2019
Survey on FPGAs in Medical Radiology Applications: Challenges, Architectures and Programming Models.
Proceedings of the International Conference on Field-Programmable Technology, 2019
Proceedings of the 37th IEEE International Conference on Computer Design, 2019
2018
Proceedings of the 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2018
Coding-aware Link Energy Estimation for 2D and 3D Networks-on-Chip with Virtual Channels.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018
Proceedings of the International Conference on Field-Programmable Technology, 2018
Proceedings of the International Conference on Field-Programmable Technology, 2018
2017
Area and power savings via asymmetric organization of buffers in 3D-NoCs for heterogeneous 3D-SoCs.
Microprocess. Microsystems, 2017
Proceedings of the 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2017
Design space exploration for a hardware-accelerated embedded real-time pose estimation using vivado HLS.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017
Proceedings of the Architecture of Computing Systems - ARCS 2017, 2017
2016
A simulation environment for design space exploration for asymmetric 3D-Network-on-Chip.
Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016
Adaptive allocation of default router paths in Network-on-Chips for latency reduction.
Proceedings of the International Conference on High Performance Computing & Simulation, 2016
2015
An optimized radix-tree for hardware-accelerated dictionary generation for semantic web databases.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015
Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs.
Proceedings of the Nordic Circuits and Systems Conference, 2015
2014
A cycle-accurate Network-on-Chip simulator with support for abstract task graph modeling.
Proceedings of the 2014 International Symposium on System-on-Chip, 2014