Rafael B. Schvittz

According to our database1, Rafael B. Schvittz authored at least 18 papers between 2015 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Evaluating the Reliability of Different Voting Schemes for Fault Tolerant Approximate Systems.
J. Electron. Test., August, 2023

Impact on Radiation Robustness of Gate Mapping in FinFET Circuits under Work-function Fluctuation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022
Improving Soft Error Robustness of Full Adder Circuits with Decoupling Cell and Transistor Sizing.
Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022

Evaluating Soft Error Reliability of Combinational Circuits Using a Monte Carlo Based Method.
Proceedings of the 23rd IEEE Latin American Test Symposium, 2022

The Impact of Logic Gates Susceptibility in Overall Circuit Reliability Analysis.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Fault Tolerance Evaluation of Different Majority Voter Designs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
Reliability Evaluation of Voters for Fault Tolerant Approximate Systems.
Proceedings of the 22nd IEEE Latin American Test Symposium, 2021

2020
Methods for Susceptibility Analysis of Logic Gates in the Presence of Single Event Transients.
Proceedings of the IEEE International Test Conference, 2020

2019
Exploring Logic Gates Layout to Improve the Accuracy of Circuit Reliability Estimation.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

A Simplified Layout-Level method for Single Event Transient Faults Susceptibility on Logic Gates.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

An Improved Technique for Logic Gate Susceptibility Evaluation of Single Event Transient Faults.
Proceedings of the VLSI-SoC: New Technology Enabler, 2019

2018
Fault masking ratio analysis of majority voters topologies.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018

Reliability evaluation of circuits designed in multi- and single-stage versions.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

Probabilistic Method for Reliability Estimation of SP- Networks considering Single Event Transient Faults.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

The Suitability of the SPR-MP Method to Evaluate the Reliability of Logic Circuits.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2016
Inserting permanent fault input dependence on PTM to improve robustness evaluation.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

A probabilistic model for stuck-on faults in combinational logic gates.
Proceedings of the 17th Latin-American Test Symposium, 2016

2015
An evaluation of BTI degradation of 32nm standard cells.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015


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