Lu Zhang
Orcid: 0000-0002-5136-1119
According to our database1,
Lu Zhang
authored at least 19 papers
between 2017 and 2024.
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Bibliography
2024
RE-Specter: Examining the Architectural Features of Configurable CNN With Power Side-Channel.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2024
ULSeq-TA: Ultra-Long Sequence Attention Fusion Transformer Accelerator Supporting Grouped Sparse Softmax and Dual-Path Sparse LayerNorm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2024
2023
Modularized Equalization Architecture With Transformer-Based Integrating Voltage Equalizer for the Series-Connected Battery Pack in Electric Bicycles.
IEEE Trans. Ind. Electron., July, 2023
A Single-Magnetic Bidirectional Integrated Equalizer Using Multi-Winding Transformer and Voltage Multiplier for Hybrid Energy Storage System.
IEEE Trans. Veh. Technol., June, 2023
Pareto Frequency-Aware Power Side-Channel Countermeasure Exploration on CNN Systolic Array.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023
A Weight-Reload-Eliminated Compute-in-Memory Accelerator for 60 fps 4K Super-Resolution.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023
An RRAM-Based Digital Computing-in-Memory Macro With Dynamic Voltage Sense Amplifier and Sparse-Aware Approximate Adder Tree.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2023
A Double-Switch Single-Transformer Integrated Equalizer for the Recycled Power Battery String of Automatic Guided Vehicles.
IEEE Trans. Ind. Electron., 2023
2022
Bit-Aware Fault-Tolerant Hybrid Retraining and Remapping Schemes for RRAM-Based Computing-in-Memory Systems.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
C-RRAM: A Fully Input Parallel Charge-Domain RRAM-based Computing-in-Memory Design with High Tolerance for RRAM Variations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
High Area/Energy Efficiency RRAM CNN Accelerator with Pattern-Pruning-Based Weight Mapping Scheme.
Proceedings of the 10th IEEE Non-Volatile Memory Systems and Applications Symposium, 2021
PETRI: Reducing Bandwidth Requirement in Smart Surveillance by Edge-Cloud Collaborative Adaptive Frame Clustering and Pipelined Bidirectional Tracking.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
2020
Memory-Based High-Level Synthesis Optimizations Security Exploration on the Power Side-Channel.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Machine-Learning-Based Side-Channel Leakage Detection in Electronic System-Level Synthesis.
IEEE Netw., 2020
High Area/Energy Efficiency RRAM CNN Accelerator with Kernel-Reordering Weight Mapping Scheme Based on Pattern Pruning.
CoRR, 2020
2018
Towards Quantified Data Analysis of Information Flow Tracking for Secure System Design.
IEEE Access, 2018
Examining the consequences of high-level synthesis optimizations on power side-channel.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
Why you should care about don't cares: Exploiting internal don't care conditions for hardware Trojans.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017