Xiumin Xu

According to our database, Xiumin Xu authored at least 16 papers between 2017 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

A Phase-Walk-Based True Random Number Generator Exploiting Dual-Ring Phase Jitter Comparison.

Liang Yao, Peiyang Kang, Jiahao Zhang, Yaohua Xu, Ying Zhang, Xiumin Xu, Huaguo Liang, Zhengfeng Huang, Yingchun Lu

IEEE Trans. Circuits Syst. II Express Briefs, March, 2026

X-RAM: a novel and efficient multi-ported memory for AI accelerator.

Xiumin Xu, Liang Yao

Integr., 2026

FTPUF:Feedback structure of TERO PUF for high reliability.

Yingchun Lu, Xinkai Wu, Jinlin Chen, Huaguo Liang, Zhengfeng Huang, Xiumin Xu, Bo Liu

Integr., 2026

Design of a dynamic obfuscation-based strong PUF resistant to modeling attacks and mutual authentication protocol.

Yingchun Lu, Hongliang Lu, Yujie Liu, Huaguo Liang, Zhengfeng Huang, Jinlin Chen, Xiumin Xu, Liang Yao

Integr., 2026

2025

TUTPFL: Triple Node Upset-Tolerant and Single-Event Transient-Filtered Low-Power Latch With HSPICE and FPGA-Based Verifications.

Aibin Yan, Jiajia Zhang, Xiumin Xu, Hanxiang Li, Na Bai, Zhengfeng Huang, Xiaolei Wang, Xiaoqing Wen, Patrick Girard

IEEE Trans. Very Large Scale Integr. Syst., October, 2025

High-Throughput TRNG Design with Novelty Adjustable TDC Based on STR.

Yongkang Feng, Liang Yao, Hongli Zhou, Minjie Wu, Shuai Xiang, Wanting Sun, Xiumin Xu, Yingchun Lu

ACM Trans. Reconfigurable Technol. Syst., June, 2025

Design of a Dynamic Obfuscation-Based Strong PUF Resistant to Modeling Attacks.

Yingchun Lu, Hongliang Lu, Yujie Liu, Huaguo Liang, Cuiyun Jiang, Zhengfeng Huang, Xiumin Xu, Liang Yao

Proceedings of the 38th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design, 2025

2018

A High Reliability FPGA Chip Identification Generator Based on PDLs.

Kai Zhou, Huaguo Liang, Yue Jiang, Zhengfeng Huang, Maoxiang Yi, Xiumin Xu, Yao Yao

Proceedings of the 27th IEEE Asian Test Symposium, 2018

An All-Digital and Jitter-Quantizing True Random Number Generator in SRAM-Based FPGAs.

Xiumin Xu, Huaguo Liang, Kai Zhou, Gaoliang Ma, Zhengfeng Huang, Maoxiang Yi, Tianming Ni, Yingchun Lu

Proceedings of the 27th IEEE Asian Test Symposium, 2018

A Low-Cost High-Efficiency True Random Number Generator on FPGAs.

Gaoliang Ma, Huaguo Liang, Liang Yao, Zhengfeng Huang, Maoxiang Yi, Xiumin Xu, Kai Zhou

Proceedings of the 27th IEEE Asian Test Symposium, 2018

2017

Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology.

Aibin Yan, Zhengfeng Huang, Maoxiang Yi, Xiumin Xu, Yiming Ouyang, Huaguo Liang

IEEE Trans. Very Large Scale Integr. Syst., 2017

A Region-Based Through-Silicon via Repair Method for Clustered Faults.

Tianming Ni, Huaguo Liang, Mu Nie, Xiumin Xu, Aibin Yan, Zhengfeng Huang

IEICE Trans. Electron., 2017

Highly Robust Double Node Upset Resilient Hardened Latch Design.

Huaguo Liang, Xin Li, Zhengfeng Huang, Aibin Yan, Xiumin Xu

IEICE Trans. Electron., 2017

A highly reliable butterfly PUF in SRAM-based FPGAs.

Xiumin Xu, Huaguo Liang, Zhengfeng Huang, Cuiyun Jiang, Yiming Ouyang, Xiangsheng Fang, Tianming Ni, Maoxiang Yi

IEICE Electron. Express, 2017

A single event transient detector in SRAM-based FPGAs.

Xiumin Xu, Huaguo Liang, Zhengfeng Huang, Cuiyun Jiang, Yingchun Lu, Aibin Yan, Tianming Ni, Maoxiang Yi

IEICE Electron. Express, 2017

Vernier ring based pre-bond through silicon vias test in 3D ICs.

Tianming Ni, Mu Nie, Huaguo Liang, Jingchang Bian, Xiumin Xu, Xiangsheng Fang, Zhengfeng Huang, Xiaoqing Wen

IEICE Electron. Express, 2017