Andrew Putnam

Orcid: 0000-0001-5241-5695

According to our database1, Andrew Putnam authored at least 26 papers between 2006 and 2020.

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In proceedings 
PhD thesis 


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What To Do With Datacenter FPGAs Besides Deep Learning.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

Introduction to the Special Section on Deep Learning in FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2018

Configurable Clouds.
IEEE Micro, 2017

KV-Direct: High-Performance In-Memory Key-Value Store with Programmable NIC.
Proceedings of the 26th Symposium on Operating Systems Principles, 2017

FPGAs in the Datacenter: Combining the Worlds of Hardware and Software Development.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Designing and Programming the Configurable Cloud.
Proceedings of the Computing Frontiers Conference, 2017

A cloud-scale acceleration architecture.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

The configurable cloud - accelerating hyperscale datacenter services with FPGAs.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

A Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services.
IEEE Micro, 2015

Accelerating Homomorphic Evaluation on Reconfigurable Hardware.
IACR Cryptol. ePrint Arch., 2015

Inspection-Resistant Memory Architectures.
IEEE Micro, 2013

How to implement effective prediction and forwarding for fusable dynamic multicore architectures.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

Inspection resistant memory: Architectural support for security from physical examination.
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

MPI as a Programming Model for High-Performance Reconfigurable Computers.
ACM Trans. Reconfigurable Technol. Syst., 2010

Dynamic vectorization in the E2 dynamic multicore architecture.
SIGARCH Comput. Archit. News, 2010

Performance and power of cache-based reconfigurable computing.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

MPI as an abstraction for software-hardware interaction for HPRCs.
Proceedings of the 2008 Second International Workshop on High-Performance Reconfigurable Computing Technology and Applications, 2008

CHiMPS: A C-level compilation flow for hybrid CPU-FPGA architectures.
Proceedings of the FPL 2008, 2008

CHiMPS: a high-level compilation flow for hybrid CPU-FPGA architectures.
Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

The WaveScalar architecture.
ACM Trans. Comput. Syst., 2007

Modeling instruction placement on a spatial architecture.
Proceedings of the SPAA 2006: Proceedings of the 18th Annual ACM Symposium on Parallelism in Algorithms and Architectures, Cambridge, Massachusetts, USA, July 30, 2006

Area-Performance Trade-offs in Tiled Dataflow Architectures.
Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006

Instruction scheduling for a tiled dataflow architecture.
Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, 2006

Reducing control overhead in dataflow architectures.
Proceedings of the 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), 2006