Matthias Hiller

Orcid: 0000-0003-1238-1114

Affiliations:
  • Technical University Munich, Germany


According to our database1, Matthias Hiller authored at least 40 papers between 2012 and 2023.

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Bibliography

2023
Structured Design and Evaluation of a Resistor-Based PUF Robust Against PVT-Variations.
Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023

VE-FIDES: Designing Trustworthy Supply Chains Using Innovative Fingerprinting Implementations.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

A Systematic Approach for Automotive Privacy Management.
Proceedings of the 7th ACM Computer Science in Cars Symposium, 2023

2021
Analysis of Communication Channels Related to Physical Unclonable Functions.
CoRR, 2021

Lightweight Authentication and Encryption for Online Monitoring in IIoT Environments.
Proceedings of the Foundations and Practice of Security - 14th International Symposium, 2021


2020
Review of error correction for PUFs and evaluation on state-of-the-art FPGAs.
J. Cryptogr. Eng., 2020

2019
Variable-Length Bit Mapping and Error-Correcting Codes for Higher-Order Alphabet PUFs - Extended Version.
J. Hardw. Syst. Secur., 2019

A Security Architecture for RISC-V based IoT Devices.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
An embedded key management system for PUF-based security enclosures.
Proceedings of the 7th Mediterranean Conference on Embedded Computing, 2018

Secure Code Execution: A Generic PUF-Driven System Architecture.
Proceedings of the Information Security - 21st International Conference, 2018

B-TREPID: Batteryless tamper-resistant envelope with a PUF and integrity detection.
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

A measurement system for capacitive PUF-based security enclosures.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Variable-Length Bit Mapping and Error-Correcting Codes for Higher-Order Alphabet PUFs.
IACR Cryptol. ePrint Arch., 2017

Take a moment and have some t: Hypothesis testing on raw PUF data.
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

Hiding Secrecy Leakage in Leaky Helper Data.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2017, 2017

2016
Key Derivation with Physical Unclonable Functions.
PhD thesis, 2016

A Lockdown Technique to Prevent Machine Learning on PUFs for Lightweight Authentication.
IEEE Trans. Multi Scale Comput. Syst., 2016

Cherry-Picking Reliable PUF Bits With Differential Sequence Coding.
IEEE Trans. Inf. Forensics Secur., 2016

Efficient Evaluation of Physical Unclonable Functions Using Entropy Measures.
J. Circuits Syst. Comput., 2016

Algebraic Security Analysis of Key Generation with Physical Unclonable Functions.
IACR Cryptol. ePrint Arch., 2016

Efficient Fuzzy Extraction of PUF-Induced Secrets: Theory and Applications.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2016, 2016

Online Reliability Testing for PUF Key Derivation.
Proceedings of the 6th International Workshop on Trustworthy Embedded Devices, 2016

2015
Secure Execution Architecture based on PUF-driven Instruction Level Code Encryption.
IACR Cryptol. ePrint Arch., 2015

Secure Sketch Metamorphosis: Tight Unified Bounds.
IACR Cryptol. ePrint Arch., 2015

Fehlerkorrekturverfahren zur sicheren Schlüsselerzeugung mit Physical Unclonable Functions.
Datenschutz und Datensicherheit, 2015

On Error Correction for Physical Unclonable Functions.
CoRR, 2015

Low-Area Reed Decoding in a Generalized Concatenated Code Construction for PUFs.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Maximum-likelihood decoding of device-specific multi-bit symbols for reliable key generation.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015

Systematic Low Leakage Coding for Physical Unclonable Functions.
Proceedings of the 10th ACM Symposium on Information, 2015

2014
Error Correction for Physical Unclonable Functions Using Generalized Concatenated Codes.
CoRR, 2014

A systematic study of lightweight hash functions on FPGAs.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

Statistic-based security analysis of ring oscillator PUFs.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Advanced performance metrics for Physical Unclonable Functions.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Seesaw: An Area-Optimized FPGA Viterbi Decoder for PUFs.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Increasing the efficiency of syndrome coding for PUFs with helper data compression.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
A new model for estimating bit error probabilities of Ring-Oscillator PUFs.
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

Breaking through fixed PUF block limitations with differential sequence coding and convolutional codes.
Proceedings of the TrustED'13, 2013

2012
Complementary IBS: Application specific error correction for PUFs.
Proceedings of the 2012 IEEE International Symposium on Hardware-Oriented Security and Trust, 2012

Reliability bound and channel capacity of IBS-based fuzzy embedders.
Proceedings of the 2012 NASA/ESA Conference on Adaptive Hardware and Systems, 2012


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