Morteza Biglari-Abhari
Orcid: 0000-0001-8094-5343
According to our database1,
Morteza Biglari-Abhari
authored at least 64 papers
between 2000 and 2023.
Collaborative distances:
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Bibliography
2023
ACM Trans. Program. Lang. Syst., June, 2023
2022
Energy-aware scheduling, compilation, and execution of hard-real-time multi-task Java programs.
Microprocess. Microsystems, November, 2022
Microprocess. Microsystems, March, 2022
2020
Fusing Appearance and Spatio-Temporal Models for Person Re-Identification and Tracking.
J. Imaging, 2020
Proceedings of the IEEE International Conference on Teaching, 2020
2019
Allocation and scheduling of SystemJ programs on chip multiprocessors with weighted TDMA scheduling.
J. Syst. Archit., 2019
J. Syst. Archit., 2019
J. Real Time Image Process., 2019
Comput. Electr. Eng., 2019
Proceedings of the 20th International Conference on Parallel and Distributed Computing, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the Architecture of Computing Systems - ARCS 2019, 2019
2018
Appl. Intell., 2018
Proceedings of the IEEE International Conference on Teaching, 2018
Proceedings of the 21st IEEE International Symposium on Real-Time Distributed Computing, 2018
Fast One-Shot Learning for Identity Classification in Person Re-identification and Tracking.
Proceedings of the 15th International Conference on Control, 2018
Proceedings of the 15th IEEE International Conference on Advanced Video and Signal Based Surveillance, 2018
2017
ACM Trans. Embed. Comput. Syst., 2017
J. Syst. Archit., 2017
Proceedings of the 2017 International Conference on Image and Vision Computing New Zealand, 2017
Proceedings of the 20th IEEE International Symposium on Real-Time Distributed Computing, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
Proceedings of the 2017 IEEE Conference on Computer Vision and Pattern Recognition Workshops, 2017
Proceedings of the IEEE International Conference on Advanced Intelligent Mechatronics, 2017
2016
A design methodology and various performance and fabrication metrics evaluation of 3D Network-on-Chip with multiplexed Through-Silicon Vias.
Microprocess. Microsystems, 2016
IEEE J. Sel. Areas Commun., 2016
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016
Proceedings of the 19th IEEE International Symposium on Real-Time Distributed Computing, 2016
Proceedings of the Trends in Applied Knowledge-Based Systems and Data Science, 2016
Proceedings of the 7th International Conference on Imaging for Crime Detection and Prevention, 2016
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016
Proceedings of the IEEE International Conference on Advanced Intelligent Mechatronics, 2016
2015
Proceedings of the 2015 IEEE Intelligent Vehicles Symposium, 2015
Proceedings of the 10th International Design & Test Symposium, 2015
2014
Modelling of Pneumatic Air Muscles for Direct Rotary Actuation of Hand Rehabilitation Glove.
Proceedings of the Social Robotics - 6th International Conference, 2014
System-Level Power and Energy Estimation Methodology for Open Multimedia Applications Platforms.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Indoor WiFi energy harvester with multiple antenna for low-power wireless applications.
Proceedings of the 23rd IEEE International Symposium on Industrial Electronics, 2014
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
2013
Proceedings of the Architecture of Computing Systems - ARCS 2013, 2013
Proceedings of the 13th International Conference on Application of Concurrency to System Design, 2013
2012
Proceedings of the Image and Vision Computing New Zealand, 2012
JOP-plus - A processor for efficient execution of java programs extended with GALS concurrency.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
Proceedings of the IEEE Ninth International Conference on Dependable, 2011
Proceedings of the 48th Design Automation Conference, 2011
2010
A Bayesian network-based framework with Constraint Satisfaction Problem (CSP) formulations for FPGA system design.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010
2009
Proceedings of the DICTA 2009, 2009
Rapid Energy Estimation for Embedded Soft-core Microprocessors.
Proceedings of the 2009 International Conference on Embedded Systems & Applications, 2009
2007
Proceedings of the Embedded Software and Systems, [Third] International Conference, 2007
2006
Microprocess. Microsystems, 2006
EURASIP J. Embed. Syst., 2006
A New Pipelined Systolic Array-Based Architecture for Matrix Inversion in FPGAs with Kalman Filter Case Study.
EURASIP J. Adv. Signal Process., 2006
2005
Customizing and extending an embedded RISC processor core for real-time video compression.
Proceedings of the Eighth International Symposium on Signal Processing and Its Applications, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005
2004
REFLIX: a processor core with native support for control-dominated embedded applications.
Microprocess. Microsystems, 2004
An optimised systolic array-based matrix inversion for rapid prototyping of Kalman filters in FPGA's.
Proceedings of the 2004 12th European Signal Processing Conference, 2004
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004
An Adaptive Superscalar Architecture for Embedded Systems.
Proceedings of the International Conference on Embedded Systems and Applications, 2004
2003
A New Reactive Processor with Architectural Support for Control Dominated Embedded Systems.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003
2002
Proceedings of the Field-Programmable Logic and Applications, 2002
2000
Improving Binary Compatibility in VLIW Machines through Compiler Assisted Dynamic Rescheduling.
Proceedings of the 26th EUROMICRO 2000 Conference, 2000