Naohito Morozumi
According to our database1,
Naohito Morozumi
authored at least 4 papers
between 2018 and 2025.
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Bibliography
2025
A 1Tb 3b/cell 3D-Flash Memory with a 29%-Improved-Energy-Efficiency Read Operation and 4.8Gb/s Power-Isolated Low-Tapped-Termination I/Os.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
Crossed Bit Line (CBL) Architecture in 3D Flash Memory CMOS Directly Bonded to Array (CBA) Structure.
Proceedings of the IEEE International Memory Workshop, 2025
2019
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018