Sanad Bushnaq

According to our database, Sanad Bushnaq authored at least 9 papers between 2009 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

A 128Gb 1-bit/Cell 96-Word-Line-Layer 3D Flash Memory to Improve the Random Read Latency With tProg = 75 μs and tR = 4 μs.

Toshiyuki Kouchi, Mami Kakoi, Noriyasu Kumazaki, Akio Sugahara, Akihiro Imamoto, Yasufumi Kajiyama, Yuri Terada, Sanad Bushnaq, Naoaki Kanagawa, Takuyo Kodama, Ryo Fukuda, Hiromitsu Komai, Norichika Asaoka, Hidekazu Ohnishi, Ryosuke Isomura, Takaya Handa, Kensuke Yamamoto, Yuki Ishizaki, Yoko Deguchi, Atsushi Okuyama, Junichi Sato, Hiroki Yabe, Cynthia Hsu, Masahiro Yoshihara

IEEE J. Solid State Circuits, 2021

inDepth: Force-based Interaction with Objects beyond A Physical Barrier.

Takatoshi Yoshida, Junichi Ogawa, Kyung Yun Choi, Sanad Bushnaq, Ken Nakagaki, Hiroshi Ishii

Proceedings of the TEI '21: Fifteenth International Conference on Tangible, 2021

2020

13.5 A 128Gb 1b/Cell 96-Word-Line-Layer 3D Flash Memory to Improve Random Read Latency with tPROG=75µs and tR=4µs.

Toshiyuki Kouchi, Noriyasu Kumazaki, Masashi Yamaoka, Sanad Bushnaq, Takuyo Kodama, Yuki Ishizaki, Yoko Deguchi, Akio Sugahara, Akihiro Imamoto, Norichika Asaoka, Ryosuke Isomura, Takaya Handa, Junichi Sato, Hiromitsu Komai, Atsushi Okuyama, Naoaki Kanagawa, Yasufumi Kajiyama, Yuri Terada, Hidekazu Ohnishi, Hiroki Yabe, Cynthia Hsu, Mami Kakoi, Masahiro Yoshihara

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2018

A 512Gb 3b/Cell 3D flash memory on a 96-word-line-layer technology.

Hiroshi Maejima, Kazushige Kanda, Susumu Fujimura, Teruo Takagiwa, Susumu Ozawa, Jumpei Sato, Yoshihiko Shindo, Manabu Sato, Naoaki Kanagawa, Junji Musha, Satoshi Inoue, Katsuaki Sakurai, Naohito Morozumi, Ryo Fukuda, Yuui Shimizu, Toshifumi Hashimoto, Xu Li, Yuki Shimizu, Kenichi Abe, Tadashi Yasufuku, Takatoshi Minamoto, Hiroshi Yoshihara, Takahiro Yamashita, Kazuhiko Satou, Takahiro Sugimoto, Fumihiro Kono, Mitsuhiro Abe, Tomoharu Hashiguchi, Masatsugu Kojima, Yasuhiro Suematsu, Takahiro Shimizu, Akihiro Imamoto, Naoki Kobayashi, Makoto Miakashi, Kouichirou Yamaguchi, Sanad Bushnaq, Hicham Haibi, Masatsugu Ogawa, Yusuke Ochi, Kenro Kubota, Taichi Wakui, Dong He, Weihan Wang, Hiroe Minagawa, Tomoko Nishiuchi, Hao Nguyen, Kwang-Ho Kim, Ken Cheah, Yee Lih Koh, Feng Lu, Venky Ramachandra, Srinivas Rajendra, Steve Choi, Keyur Payak, Namas Raghunathan, Spiros Georgakis, Hiroshi Sugawara, Seungpil Lee, Takuya Futatsuyama, Koji Hosono, Noboru Shibata, Toshiki Hisada, Tetsuya Kaneko, Hiroshi Nakamura

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2012

All-Digital Wireless Transceiver with Sub-Sampling Demodulation and Burst-Error Correction.

Sanad Bushnaq, Makoto Ikeda, Kunihiro Asada

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

All-digital tunable power amplifier consuming 0.03mW/MHz using 0.18µm CMOS.

Sanad Bushnaq, Makoto Ikeda, Kunihiro Asada

IEICE Electron. Express, 2012

Range extension of inductive coupling communication using multi-stage resonance.

Sanad Bushnaq, Makoto Ikeda, Kunihiro Asada

Proceedings of the International Symposium on Communications and Information Technologies, 2012

2011

All-digital 400∼900 MHz power amplifier consuming 0.03 mW/MHz using 0.18 μm CMOS.

Sanad Bushnaq, Makoto Ikeda, Kunihiro Asada

Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

2009

All digital baseband 50 Mbps data recovery using 5× oversampling with 0.9 data unit interval clock jitter tolerance.

Sanad Bushnaq, Toru Nakura, Makoto Ikeda, Kunihiro Asada

Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009