Chintan Thakkar

According to our database1, Chintan Thakkar authored at least 18 papers between 2006 and 2020.

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Bibliography

2020
4.5 A 64Gb/s 1.4pJ/b/element 60GHz 2×2-Element Phased-Array Receiver with 8b/symbol Polarization MIMO and Spatial Interference Tolerance.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
A 42.2-Gb/s 4.3-pJ/b 60-GHz Digital Transmitter With 12-b/Symbol Polarization MIMO.
IEEE J. Solid State Circuits, 2019

A 42.2Gb/s 4.3pJ/b 60GHz Digital Transmitter with 12b/Symbol Polarization MIMO.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
A 60-GHz Transceiver and Baseband With Polarization MIMO in 28-nm CMOS.
IEEE J. Solid State Circuits, 2018

A 40Gb/s 6pJ/b RX baseband in 28nm CMOS for 60GHz polarization MIMO.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A 27.8Gb/s 11.5pJ/b 60GHz transceiver in 28nm CMOS with polarization MIMO.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

High-speed contactless I/O for computing devices.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2017
A 25 Gb/s 60 GHz digital power amplifier in 28nm CMOS.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

2016
A 32 Gb/s Bidirectional 4-channel 4 pJ/b Capacitively Coupled Link in 14 nm CMOS for Proximity Communication.
IEEE J. Solid State Circuits, 2016

23.2 A 32Gb/s bidirectional 4-channel 4pJ/b capacitively coupled link in 14nm CMOS for proximity communication.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2014
Design Techniques for a Mixed-Signal I/Q 32-Coefficient Rx-Feedforward Equalizer, 100-Coefficient Decision Feedback Equalizer in an 8 Gb/s 60 GHz 65 nm LP CMOS Receiver.
IEEE J. Solid State Circuits, 2014

2013
A mixed-signal 32-coefficient RX-FFE 100-coefficient DFE for an 8Gb/s 60GHz receiver in 65nm LP CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
Design of Multi-Gb/s Multi-Coefficient Mixed-Signal Equalizers.
PhD thesis, 2012

A 10 Gb/s 45 mW Adaptive 60 GHz Baseband in 65 nm CMOS.
IEEE J. Solid State Circuits, 2012

A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface.
IEEE J. Solid State Circuits, 2012

2009
A 90 nm CMOS Low-Power 60 GHz Transceiver With Integrated Baseband Circuitry.
IEEE J. Solid State Circuits, 2009

A 90nm CMOS low-power 60GHz transceiver with integrated baseband circuitry.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2006
SWISH: semantic analysis of window titles and switching history.
Proceedings of the 11th International Conference on Intelligent User Interfaces, 2006


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