Srivatsa Rangachar Srinivasa

Orcid: 0000-0002-3146-6642

According to our database1, Srivatsa Rangachar Srinivasa authored at least 20 papers between 2009 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

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Bibliography

2023
On Continuing DNN Accelerator Architecture Scaling Using Tightly Coupled Compute-on-Memory 3-D ICs.
IEEE Trans. Very Large Scale Integr. Syst., October, 2023

2022
Design Methodology for Scalable 2.5D/3D Heterogenous Tiled Chiplet Systems.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

2021
Cryogenic Memory Technologies.
CoRR, 2021

Trends and Opportunities for SRAM Based In-Memory and Near-Memory Computation.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

CAPE: A Content-Addressable Processing Engine.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

A 93 TOPS/Watt Near-Memory Reconfigurable SAD Accelerator for HEVC/AV1/JEM Encoding.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
Look-Up Table based Energy Efficient Processing in Cache Support for Neural Network Acceleration.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

2019
ROBIN: Monolithic-3D SRAM for Enhanced Robustness with In-Memory Computation Support.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Recent Advances in Compute-in-Memory Support for SRAM Using Monolithic 3-D Integration.
IEEE Micro, 2019

Back-End-of-Line Compatible Transistors for Monolithic 3-D Integration.
IEEE Micro, 2019

Monolithic-3D Integration Augmented Design Techniques for Computing in SRAMs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
Compact 3-D-SRAM Memory With Concurrent Row and Column Data Access Capability Using Sequential Monolithic 3-D Integration.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Symmetric 2-D-Memory Access to Multidimensional Data.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Harnessing Emerging Technology for Compute-in-Memory Support.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

A Power-Efficient Hybrid Architecture Design for Image Recognition Using CNNs.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

A Monolithic-3D SRAM Design with Enhanced Robustness and In-Memory Computation Support.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

Emerging reconfigurable nanotechnologies: can they support future electronics?
Proceedings of the International Conference on Computer-Aided Design, 2018

2017
Improving FPGA Design with Monolithic 3D Integration Using High Dense Inter-Stack Via.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Spendthrift: Machine learning based resource and frequency scaling for ambient energy harvesting nonvolatile processors.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2009
Hardware implementation low power high speed FFT core.
Int. Arab J. Inf. Technol., 2009


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