Qing'an Li

According to our database¹, Qing'an Li authored at least 33 papers between 2010 and 2020.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of three.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Other

Bibliography

2020

Loop2Recursion: Compiler-Assisted Wear Leveling for Non-Volatile Memory.

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE International Conference on Computer Design, 2020

2019

Memory-aware TLP throttling and cache bypassing for GPUs.

[BibT_eX]

[DOI]

Clust. Comput., 2019

Reuse locality aware cache partitioning for last-level cache.

[BibT_eX]

[DOI]

Comput. Electr. Eng., 2019

Checkpointing-aware Data Allocation for Energy Harvesting Powered Non-volatile Processors.

[BibT_eX]

[DOI]

Fuyang Li

Qing'an Li

Chun Jason Xue

Proceedings of the 2019 IEEE Non-Volatile Memory Systems and Applications Symposium, 2019

A Wear Leveling Aware Memory Allocator for Both Stack and Heap Management in PCM-based Main Memory Systems.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2017

Stack-Size Sensitive On-Chip Memory Backup for Self-Powered Nonvolatile Processors.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

2016

Write Mode Aware Loop Tiling for High Performance Low Power Volatile PCM in Embedded Systems.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

2015

Compiler-Assisted Refresh Minimization for Volatile STT-RAM Cache.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2015

物联网环境中数据存储与查询机制研究 (Data Storage and Query in Internet of Things).

[BibT_eX]

[DOI]

计算机科学, 2015

Software assisted non-volatile register reduction for energy harvesting based cyber-physical system.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Compiler directed automatic stack trimming for efficient non-volatile processors.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

A Unified Write Buffer Cache Management Scheme for Flash Memory.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Compiler-Assisted STT-RAM-Based Hybrid Cache for Energy Efficient Embedded Systems.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

WCET-Aware Re-Scheduling Register Allocation for Real-Time Embedded Systems With Clustered VLIW Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Thread Progress Aware Coherence Adaption for Hybrid Cache Coherence Protocols.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2014

Migration-Aware Loop Retiming for STT-RAM-Based Hybrid Cache in Embedded Systems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A wear-leveling-aware dynamic stack for PCM memory in embedded systems.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Write Mode Aware Loop Tiling for High Performance Low Power Volatile PCM.

[BibT_eX]

[DOI]

Keni Qiu

Qing'an Li

Chun Jason Xue

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

Task Allocation on Nonvolatile-Memory-Based Hybrid Main Memory.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Low-energy volatile STT-RAM cache design using cache-coherence-enabled adaptive refresh.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2013

Compiler directed write-mode selection for high performance low power volatile PCM.

[BibT_eX]

[DOI]

Proceedings of the SIGPLAN/SIGBED Conference on Languages, 2013

Cache coherence enabled adaptive refresh for volatile STT-RAM.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Minimizing code size via page selection optimization on partitioned memory architectures.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Compilers, 2013

2012

Compiler-assisted preferred caching for embedded systems with STT-RAM based hybrid cache.

[BibT_eX]

[DOI]

Proceedings of the SIGPLAN/SIGBED Conference on Languages, 2012

Code Motion for Migration Minimization in STT-RAM Based Hybrid Cache.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

MAC: migration-aware compilation for STT-RAM based hybrid cache in embedded systems.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

TEACA: Thread ProgrEss Aware Coherence Adaption for hybrid coherence protocols.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th Symposium on Embedded Systems for Real-time Multimedia, 2012

MGC: Multiple graph-coloring for non-volatile memory based hybrid Scratchpad Memory.

[BibT_eX]

[DOI]

Proceedings of the 16th Workshop on Interaction between Compilers and Computer Architectures, 2012

2011

Minimizing Schedule Length via Cooperative Register Allocation and Loop Scheduling for Embedded Systems.

[BibT_eX]

[DOI]

Yazhi Huang

Qing'an Li

Chun Jason Xue

Proceedings of the IEEE 10th International Conference on Trust, 2011

Game Model Based Register Allocation.

[BibT_eX]

[DOI]

Proceedings of the Applied Informatics and Communication - International Conference, 2011

2010

A Heuristic Algorithm for optimizing Page Selection Instructions

[BibT_eX]

[DOI]

CoRR, 2010

Integer Promotion Elimination on Abstract Syntax Tree.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International Conference on Computer and Information Technology, 2010

Qing'an Li

Timeline

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