Robert M. Radway

According to our database1, Robert M. Radway authored at least 8 papers between 2019 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2023
Foundry Monolithic 3D BEOL Transistor + Memory Stack: Iso-performance and Iso-footprint BEOL Carbon Nanotube FET+RRAM vs. FEOL Silicon FET+RRAM.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Testbench on a Chip: A Yield Test Vehicle for Resistive Memory Devices.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

PBA: Percentile-Based Level Allocation for Multiple-Bits-Per-Cell RRAM.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Ultra-Dense 3D Physical Design Unlocks New Architectural Design Points with Large Benefits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Thermal Scaffolding for Ultra-Dense 3D Integrated Circuits.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
Three-Dimensional Stacked Neural Network Accelerator Architectures for AR/VR Applications.
IEEE Micro, 2022

CHIMERA: A 0.92-TOPS, 2.2-TOPS/W Edge AI Accelerator With 2-MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference.
IEEE J. Solid State Circuits, 2022

2019
A 43pJ/Cycle Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019


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