Kazuhiko Iwasaki

According to our database, Kazuhiko Iwasaki authored at least 60 papers between 1986 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2018

Layout-Aware Fast Bridge/Open Test Generation by 2-Step Pattern Reordering.

Masayuki Arai, Shingo Inuyama, Kazuhiko Iwasaki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

2017

Reordering-Based Test Pattern Reduction Considering Critical Area-Aware Weighted Fault Coverage.

Masayuki Arai, Kazuhiko Iwasaki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Layout-aware 2-step window-based pattern reordering for fast bridge/open test generation.

Masayuki Arai, Shingo Inuyama, Kazuhiko Iwasaki

Proceedings of the IEEE International Test Conference, 2017

2016

Critical-Area-Aware Test Pattern Generation and Reordering.

Shingo Inuyama, Masayuki Arai, Kazuhiko Iwasaki

Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015

Note on Fast Bridge Fault Test Generation Based on Critical Area.

Masayuki Arai, Shingo Inuyama, Kazuhiko Iwasaki

Proceedings of the Algorithms and Architectures for Parallel Processing, 2015

2013

Checkpoint Time Arrangement Rotation in Hybrid State Saving with a Limited Number of Periodical Checkpoints.

Ryo Suzuki, Mamoru Ohara, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki

IEICE Trans. Inf. Syst., 2013

Classification of DNS Queries for Anomaly Detection.

Hongbo Shi, Kazuhiko Iwasaki

Proceedings of the IEEE 19th Pacific Rim International Symposium on Dependable Computing, 2013

2012

Note on Layout-Aware Weighted Probabilistic Bridge Fault Coverage.

Masayuki Arai, Yoshihiro Shimizu, Kazuhiko Iwasaki

Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011

Area-Per-Yield and Defect Level of Cascaded TMR for Pipelined Processors.

Masayuki Arai, Kazuhiko Iwasaki

Proceedings of the 17th IEEE Pacific Rim International Symposium on Dependable Computing, 2011

2010

Reduction of Test Data Volume and Improvement of Diagnosability Using Hybrid Compression.

Anis Uzzaman, Brion L. Keller, Brian Foutz, Sandeep Bhatia, Thomas Bartenstein, Masayuki Arai, Kazuhiko Iwasaki

IEICE Trans. Inf. Syst., 2010

Reduction of Area per Good Die for SoC Memory Built-In Self-Test.

Masayuki Arai, Tatsuro Endo, Kazuhiko Iwasaki, Michinobu Nakao, Iwao Suzuki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

A Distributed Data Replication Protocol for File Versioning with Optimal Node Assignments.

Takahiko Ikeda, Mamoru Ohara, Satoshi Fukumoto, Masayuki Arai, Kazuhiko Iwasaki

Proceedings of the 16th IEEE Pacific Rim International Symposium on Dependable Computing, 2010

2009

Automatic Handling of Programmable On-Product Clock Generation (OPCG) Circuitry for Low Power Aware Delay Test.

Anis Uzzaman, Brion L. Keller, Thomas J. Snethen, Kazuhiko Iwasaki, Masayuki Arai

J. Low Power Electron., 2009

Small Delay Fault Model for Intra-Gate Resistive Open Defects.

Masayuki Arai, Akifumi Suto, Kazuhiko Iwasaki, Katsuyuki Nakano, Michihiro Shintani, Kazumi Hatayama, Takashi Aikyo

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

2008

Tester Structure Expression Language and Its Application to the Environment for VLSI Tester Program Development.

Masayuki Sato, Hiroki Wakamatsu, Masayuki Arai, Kenichi Ichino, Kazuhiko Iwasaki, Takeshi Asakawa

J. Inf. Process. Syst., 2008

Analysis of Probabilistic Trapezoid Protocol for Data Replication.

Tabito Suzuki, Mamoru Ohara, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki

J. Inf. Process., 2008

Test Data Compression for Scan-Based BIST Aiming at 100x Compression Rate.

Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, Tatsuru Matsuo, Takahisa Hiraide, Hideaki Konishi, Michiaki Emori, Takashi Aikyo

IEICE Trans. Inf. Syst., 2008

Study on Test Data Reduction Combining Illinois Scan and Bit Flipping.

Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki

IEICE Trans. Inf. Syst., 2008

Study on Expansion of Convolutional Compactors over Galois Field.

Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki

IEICE Trans. Inf. Syst., 2008

Hardware Overhead Reduction for Memory BIST.

Masayuki Arai, Kazuhiko Iwasaki, Michinobu Nakao, Iwao Suzuki

Proceedings of the 2008 IEEE International Test Conference, 2008

2006

Analytical Model on Hybrid State Saving with a Limited Number of Checkpoints and Bound Rollbacks.

Mamoru Ohara, Ryo Suzuki, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Extension of coefficients for (n, k, m) convolutional-code-based packet loss recovery.

Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki

Comput. Math. Appl., 2006

Test Data Compression of 100x for Scan-Based BIST.

Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, Tatsuru Matsuo, Takahisa Hiraide, Hideaki Konishi, Michiaki Emori, Takashi Aikyo

Proceedings of the 2006 IEEE International Test Conference, 2006

Expansion of Convolutional Compactors over Galois Field.

Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki

Proceedings of the 15th Asian Test Symposium, 2006

2005

Reliability Analysis of a Convolutional-Code-Based Packet Level FEC under Limited Buffer Size.

Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Analysis of error-masking and X-masking probabilities for convolutional compactors.

Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

2004

Technique to Diagnose Open Defects that Takes Coupling Effects into Consideration.

Yasuo Sato, Iwao Yamazaki, Hiroki Yamanaka, Toshio Ikeda, Masahiro Takakura, Kazuhiko Iwasaki

IEICE Trans. Inf. Syst., 2004

Application of Partially Rotational Scan Technique with Tester IP for Processor Circuits.

Kenichi Ichino, Ko-ichi Watanabe, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki

IEICE Trans. Inf. Syst., 2004

Analysis of Read and Write Availability for Generalized Hybrid Data Replication Protocol.

Masayuki Arai, Tabito Suzuki, Mamoru Ohara, Satoshi Fukumoto, Kazuhiko Iwasaki, Hee Yong Youn

Proceedings of the 10th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2004), 2004

Finding a Recovery Line in Uncoordinated Checkpointing.

Mamoru Ohara, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki

Proceedings of the 24th International Conference on Distributed Computing Systems Workshops (ICDCS 2004 Workshops), 2004

Seed Selection Procedure for LFSR-Based BIST with Multiple Scan Chains and Phase Shifters.

Masayuki Arai, Harunobu Kurokawa, Kenichi Ichino, Satoshi Fukumoto, Kazuhiko Iwasaki

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003

BIST-oriented test pattern generator for detection of transition faults.

Takeshi Asakawa, Kazuhiko Iwasaki, Seiji Kajihara

Syst. Comput. Jpn., 2003

Seed Selection Procedure for LFSR-Based Random Pattern Generators.

Kenichi Ichino, Ko-ichi Watanabe, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

Implementation of Memory Tester Consisting of SRAM-Based Reconfigurable Cells.

Yuki Yamagata, Kenichi Ichino, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, Masayuki Satoh, Hiroyuki Itabashi, Takashi Murai, Nobuyuki Otsuka

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

Evaluation of Convolutional-Code-Based FEC under Limited Recovery Time and Its Application to Real-time Transmission.

Masayuki Arai, Hitoshi Kurosu, Satoshi Fukumoto, Kazuhiko Iwasaki

Proceedings of the 9th Pacific Rim International Symposium on Dependable Computing (PRDC 2002), 2002

Adaptive Checkpointing for Time Warp Technique with a Limited Number of Checkpoints.

Ryo Suzuki, Satoshi Fukumoto, Kazuhiko Iwasaki

Proceedings of the 22nd International Conference on Distributed Computing Systems, 2002

Experiment for High-Assurance Video Conference System over the Internet.

Masayuki Arai, Hitoshi Kurosu, Mamoru Ohara, Ryo Suzuki, Satoshi Fukumoto, Kazuhiko Iwasaki

Proceedings of the 7th IEEE International Symposium on High-Assurance Systems Engineering (HASE 2002), 2002

2001

Using ATPG vectors for BIST test pattern generator.

Takeshi Asakawa, Kazuhiko Iwasaki

Syst. Comput. Jpn., 2001

Analysis of Using Convolutional Codes to Recover Packet Losses over Burst Erasure Channels.

Masayuki Arai, Anna Yamamoto, Anna Yamaguchi, Satoshi Fukumoto, Kazuhiko Iwasaki

Proceedings of the 8th Pacific Rim International Symposium on Dependable Computing (PRDC 2001), 2001

Hybrid BIST Using Partially Rotational Scan.

Kenichi Ichino, Takeshi Asakawa, Satoshi Fukumoto, Kazuhiko Iwasaki, Seiji Kajihara

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000

Evaluation of multicast error recovery using convolutional codes.

Anna Yamaguchi, Masayuki Arai, Kazuhiko Iwasaki

Proceedings of the 2000 Pacific Rim International Symposium on Dependable Computing (PRDC 2000), 2000

Method to Recover Internet Packet Losses Using (n, n - 1, m) Convolutional Codes.

Masayuki Arai, Anna Yamaguchi, Kazuhiko Iwasaki

Proceedings of the 2000 International Conference on Dependable Systems and Networks (DSN 2000) (formerly FTCS-30 and DCCA-8), 2000

1999

Measurement and Modeling of Burst Packet Losses in Internet End-to-End Communications.

Masayuki Arai, Atsushi Chiba, Kazuhiko Iwasaki

Proceedings of the 1999 Pacific Rim International Symposium on Dependable Computing (PRDC 1999), 1999

1997

Experimental fault analysis of 1 Mb SRAM chips.

Hiroyuki Goto, Shigeo Nakamura, Kazuhiko Iwasaki

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

1996

Aliasing Error for a Mask ROM Built-In Self-Test.

Kazuhiko Iwasaki, Shigeo Nakamura

IEEE Trans. Computers, 1996

1995

On the Maximum Value of Aliasing Probabilities for Single Input Signature Registers.

Shou-ping Feng, Toru Fujiwara, Tadao Kasami, Kazuhiko Iwasaki

IEEE Trans. Computers, 1995

1994

A Concurrent Test Architecture for Massively Parallel Computers and Its Error Detection Capability.

Marius V. A. Hâncu, Kazuhiko Iwasaki, Yuji Sato, Mamoru Sugie

IEEE Trans. Parallel Distributed Syst., 1994

Aliasing error for a mask ROM built-in self-test.

Kazuhiko Iwasaki, Akinori Furuta, Shigeo Nakamura

Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

1993

A Note on Aliasing Probability for Multiple Input Signature Analyzer.

Masakatu Morii, Kazuhiko Iwasaki

IEEE Trans. Computers, 1993

A uniform network for VLSI massively parallel computers.

Kazuhiko Iwasaki, Christian Iseli, Yuji Sato

Syst. Comput. Jpn., 1993

1992

Experimental results on the error detection capability of a concurrent test architecture for massively-parallel computers.

Marius V. A. Hâncu, Kazuhiko Iwasaki, Yuji Sato, Mamoru Sugie

Parallel Comput., 1992

A defect-tolerant design for mask ROMs.

Kazuhiko Iwasaki, Toru Fujiwara, Tadao Kasami

Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

1990

An analysis of the aliasing probability of multiple-input signature registers in the case of a 2^m-ary symmetric channel.

Kazuhiko Iwasaki, Fumio Arakawa

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Analysis of Fault Detection Probability of CMOS Combinational Circuits and Its Application to Signature Testing.

Kazuhiko Iwasaki

Syst. Comput. Jpn., 1990

Design of signature circuits based on weight distributions of error-correcting codes.

Kazuhiko Iwasaki, Noboru Yamaguchi

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

1989

Aliasing Probabilities and Weight Distributions of Several Codes.

Kazuhiko Iwasaki, Tadahiko Nishimukai

Syst. Comput. Jpn., 1989

1988

Analysis and proposal of signature circuits for LSI testing.

Kazuhiko Iwasaki

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

Cache-based pipeline architecture in the Hitachi H32/200 32-bit microprocessor.

Tadahiko Nishimukai, Hideo Inayoshi, Kikuko Takagi, Kazuhiko Iwasaki, Ikuya Kawasaki, M. Hanawa, Takeshi Okada

Proceedings of the Computer Design: VLSI in Computers and Processors, 1988

1987

Decoding method for shortened fire codes and its application to VLSI processor.

Kazuhiko Iwasaki, Tsuneo Funabashi, Tatsuaki Ueno

Syst. Comput. Jpn., 1987

1986

Analysis of error-detecting probability of signature circuit for lsi self-testing and proprosal of new signature circuit.

Kazuhiko Iwasaki, Noboru Yamaguchi, Yoshimune Hagiwara

Syst. Comput. Jpn., 1986