Seth H. Pugsley

According to our database1, Seth H. Pugsley authored at least 13 papers between 2008 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

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Bibliography

2022
The Championship Simulator: Architectural Simulation for Education and Competition.
CoRR, 2022

2019
Perceptron-based prefetch filtering.
Proceedings of the 46th International Symposium on Computer Architecture, 2019

2017
Kill the Program Counter: Reconstructing Program Behavior in the Processor Cache Hierarchy.
Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, 2017

2016
Path confidence based lookahead prefetching.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

2015
Opportunities for Near Data Computing in MapReduce Workloads.
PhD thesis, 2015

Efficiently prefetching complex address patterns.
Proceedings of the 48th International Symposium on Microarchitecture, 2015

Fixed-function hardware sorting accelerators for near data MapReduce execution.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

2014
Comparing Implementations of Near-Data Computing with In-Memory MapReduce Workloads.
IEEE Micro, 2014

NDC: Analyzing the impact of 3D-stacked memory+logic devices on MapReduce workloads.
Proceedings of the 2014 IEEE International Symposium on Performance Analysis of Systems and Software, 2014

Memory bandwidth reservation in the cloud to avoid information leakage in the memory controller.
Proceedings of the HASP 2014, 2014

Sandbox Prefetching: Safe run-time evaluation of aggressive prefetchers.
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

2010
SWEL: hardware cache coherence protocols to map shared data onto shared caches.
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

2008
Scalable and reliable communication for hardware transactional memory.
Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, 2008


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