Stanley Chen

According to our database, Stanley Chen authored at least 10 papers between 2012 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET.

Jay Im, Kevin Zheng, Chuen-Huei Adam Chou, Lei Zhou, Jae Wook Kim, Stanley Chen, Yipeng Wang, Hao-Wei Hung, Kee Hian Tan, Winson Lin, Arianne Roldan, Declan Carey, Ilias Chlis, Ronan Casey, Ade Bekele, Ying Cao, David Mahashin, Hong Ahn, Hongtao Zhang, Yohan Frans, Ken Chang

IEEE J. Solid State Circuits, 2021

2020

6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET.

Jay Im, Kevin Zheng, Adam Chou, Lei Zhou, Jae Wook Kim, Stanley Chen, Yipeng Wang, Hao-Wei Hung, Kee Hian Tan, Winson Lin, Arianne Roldan, Declan Carey, Ilias Chlis, Ronan Casey, Ade Bekele, Ying Cao, David Mahashin, Hong Ahn, Hongtao Zhang, Yohan Frans, Ken Chang

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2018

A 0.5-28GB/S Wireline Tranceiver with 15-Tap DFE and Fast-Locking Digital CDR in 7NM FinFET.

Jay Im, Stanley Chen, Dave Freitas, Adam Chou, Lei Zhou, Ian Zhuang, Tim Cronin, David Mahashin, Winson Lin, Kok Lim Chan, Hongyuan Zhao, Kee Hian Tan, Ade Bekele, Didem Turker, Parag Upadhyaya, Yohan Frans, Ken Chang

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 4-to-16GHz inverter-based injection-locked quadrature clock generator with phase interpolators for multi-standard I/Os in 7nm FinFET.

Stanley Chen, Lei Zhou, Ian Zhuang, Jay Im, Didem Turkur Melek, Jinyung Namkoong, Mayank Raj, Jaewook Shin, Yohan Frans, Ken Chang

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017

A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET.

Jay Im, Dave Freitas, Arianne Roldan, Ronan Casey, Stanley Chen, Adam Chou, Tim Cronin, Kevin Geary, Scott McLeod, Lei Zhou, Ian Zhuang, Jaeduk Han, Sen Lin, Parag Upadhyaya, Geoff Zhang, Yohan Frans, Ken Chang

IEEE J. Solid State Circuits, 2017

6.3 A 40-to-56Gb/s PAM-4 receiver with 10-tap direct decision-feedback equalization in 16nm FinFET.

Jay Im, Dave Freitas, Arianne Roldan, Ronan Casey, Stanley Chen, Adam Chou, Tim Cronin, Kevin Geary, Scott McLeod, Lei Zhou, Ian Zhuang, Jaeduk Han, Sen Lin, Parag Upadhyaya, Geoff Zhang, Yohan Frans, Ken Chang

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016

A fully-adaptive wideband 0.5-32.75Gb/s FPGA transceiver in 16nm FinFET CMOS technology.

Parag Upadhyaya, Ade Bekele, Didem Turkur Melek, Haibing Zhao, Jay Im, Junho Cho, Kee Hian Tan, Scott McLeod, Stanley Chen, Wenfeng Zhang, Yohan Frans, Ken Chang

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2015

3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS.

Parag Upadhyaya, Jafar Savoj, Fu-Tai An, Ade Bekele, Anup P. Jose, Bruce Xu, Zhaoyin Daniel Wu, Didem Turker, Hesam Amir Aslanzadeh, Hiva Hedayati, Jay Im, Siok-Wei Lim, Stanley Chen, Toan Pham, Yohan Frans, Ken Chang

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014

2.8 A pulse-position-modulation phase-noise-reduction technique for a 2-to-16GHz injection-locked ring oscillator in 20nm CMOS.

Jun-Chau Chien, Parag Upadhyaya, Howard Jung, Stanley Chen, Wayne Fang, Ali M. Niknejad, Jafar Savoj, Ken Chang

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2012

A wide common-mode fully-adaptive multi-standard 12.5Gb/s backplane transceiver in 28nm CMOS.

Jafar Savoj, Kenny C.-H. Hsieh, Parag Upadhyaya, Fu-Tai An, Ade Bekele, Stanley Chen, Xuewen Jiang, Kang Wei Lai, Chi Fung Poon, Aman Sewani, Didem Turker, Karthik Venna, Zhaoyin Daniel Wu, Bruce Xu, Elad Alon, Ken Chang

Proceedings of the Symposium on VLSI Circuits, 2012