Stephen T. Quay

According to our database1, Stephen T. Quay authored at least 20 papers between 1999 and 2018.

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Bibliography

2018
Interconnect Optimization Considering Multiple Critical Paths.
Proceedings of the 2018 International Symposium on Physical Design, 2018

2008
Fast interconnect synthesis with layer assignment.
Proceedings of the 2008 International Symposium on Physical Design, 2008

2007
Techniques for Fast Physical Synthesis.
Proc. IEEE, 2007

The nuts and bolts of physical synthesis.
Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007

Probabilistic Congestion Prediction with Partial Blockages.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Fast Electrical Correction Using Resizing and Buffering.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2004
Porosity-aware buffered Steiner tree construction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

A fast algorithm for identifying good buffer insertion candidate locations.
Proceedings of the 2004 International Symposium on Physical Design, 2004

Fast and flexible buffer trees that navigate the physical layout environment.
Proceedings of the 41th Design Automation Conference, 2004

2003
Buffer insertion with adaptive blockage avoidance.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Porosity aware buffered steiner tree construction.
Proceedings of the 2003 International Symposium on Physical Design, 2003

2002
Correction to "interconnect synthesis without wire tapering".
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

2001
Steiner tree optimization for buffers, blockages, and bays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Interconnect synthesis without wire tapering.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Buffered Steiner trees for difficult instances.
Proceedings of the 2001 International Symposium on Physical Design, 2001

2000
Buffer Library Selection.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

1999
Buffer insertion for noise and delay optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Is wire tapering worthwhile?
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Buffer Insertion with Accurate Gate and Interconnect Delay Computation.
Proceedings of the 36th Conference on Design Automation, 1999


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