Gabriele Filipponi

Orcid: 0000-0002-1436-3764

According to our database1, Gabriele Filipponi authored at least 10 papers between 2022 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
Netlist-Independent Functional Stress Pattern Generation Strategy for AI HW Accelerators Embedded into SoCs.
IEEE Trans. Computers, February, 2026


2025
A System-Level Test Methodology for Communication Peripherals in System-on-Chips.
IEEE Trans. Computers, February, 2025

Enhancing Logic Diagnosis of Field Returns Through Logic BIST in Automotive SoCs.
Proceedings of the 26th IEEE Latin American Test Symposium, 2025

FSWGEN: a Device-tree Specification driven System-Level Test workload generator.
Proceedings of the IEEE International Test Conference, 2025

2023
Low cost external serial interface watchdog for SoCs and FPGAs automatic characterization tests.
Proceedings of the 24th IEEE Latin American Test Symposium, 2023

Collecting diagnostic information through dichotomic search from Logic BIST of failing in-field automotive SoCs with delay faults.
Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023

2022
In-field Data Collection System through Logic BIST for large Automotive Systems-on-Chip.
Proceedings of the IEEE International Test Conference, 2022

An Optimized Burn-In Stress Flow targeting Interconnections logic to Embedded Memories in Automotive Systems-on-Chip.
Proceedings of the IEEE European Test Symposium, 2022

Online scheduling of concurrent Memory BISTs execution at Real-Time Operating-System level.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022


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