Salvatore Pappalardo

Orcid: 0009-0001-4812-5908

According to our database1, Salvatore Pappalardo authored at least 22 papers between 2010 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
OpRA: Optimizing Resiliency Assessment for Deep Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2026

Benchmark Suite for Resilience Assessment of Deep Learning Models.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2026

Special Session: Reliability Assessment of DNN Models and Inference on Systolic Arrays.
Proceedings of the 44th IEEE VLSI Test Symposium, 2026


Case Study: Improving the Robustness of Photonic Neural Networks Against Memory Faults.
Proceedings of the 27th IEEE Latin American Test Symposium, 2026

2025
Reliability of Deep Neural Networks: Impact and Open Issues.
IEEE Des. Test, June, 2025

SAFFIRA A Framework for Assessing the Reliability of Systolic-Array DNN Accelerators.
J. Circuits Syst. Comput., 2025

Special Session: Trustworthy Hardware-AI at the Cloud.
Proceedings of the 43rd IEEE VLSI Test Symposium, 2025

A Benchmark Suite to Evaluate DNN's Resilience.
Proceedings of the IEEE International Test Conference, 2025

AxEnMULT: Design of an Efficient and Reliable Approximate Encoding-Based Multiplier.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2025

2024
Delineating citrus management zones using spatial interpolation and UAV-based multispectral approaches.
Comput. Electron. Agric., 2024


Heterogeneous Approximation of DNN HW Accelerators based on Channels Vulnerability.
Proceedings of the 32nd IFIP/IEEE International Conference on Very Large Scale Integration, 2024


Reliable and Efficient hardware for Trustworthy Deep Neural Networks.
Proceedings of the IEEE International Conference on Design, 2024

How Systolic Array Dataflow impacts on the resilience to hardware faults.
Proceedings of the IEEE International Conference on Design, 2024

SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN Accelerators.
Proceedings of the 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems, 2024

2023
A Fault Injection Framework for AI Hardware Accelerators.
Proceedings of the 24th IEEE Latin American Test Symposium, 2023

Input-aware accuracy characterization for approximate circuits.
Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2023

Investigating the effect of approximate multipliers on the resilience of a systolic array DNN accelerator.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

Resilience-Performance Tradeoff Analysis of a Deep Neural Network Accelerator.
Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023

2010
Participatory approach to the reduction of the digital gap in Amazon region of Ecuador in the framework of the "Innovation for Development" program.
Proceedings of the 2010 ITU-Kaleidoscope: Beyond the Internet?, 2010


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