Surendra Hemaram
Orcid: 0000-0001-5623-8358
  According to our database1,
  Surendra Hemaram
  authored at least 10 papers
  between 2021 and 2025.
  
  
Collaborative distances:
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Bibliography
  2025
    IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2025
    
  
    Proceedings of the IEEE European Test Symposium, 2025
    
  
    Proceedings of the IEEE European Test Symposium, 2025
    
  
    Proceedings of the Design, Automation & Test in Europe Conference, 2025
    
  
  2024
NN-ECC: Embedding Error Correction Codes in Neural Network Weight Memories using Multi-task Learning.
    
  
    Proceedings of the 42nd IEEE VLSI Test Symposium, 2024
    
  
    Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024
    
  
  2023
A Low Overhead Checksum Technique for Error Correction in Memristive Crossbar for Deep Learning Applications.
    
  
    Proceedings of the 41st IEEE VLSI Test Symposium, 2023
    
  
  2022
    Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022
    
  
  2021
Optimal Design of a Decoupling Network Using Variants of Particle Swarm Optimization Algorithm.
    
  
    Proceedings of the IEEE International Symposium on Circuits and Systems, 2021