Takashi Nishida

According to our database, Takashi Nishida authored at least 15 papers between 1989 and 2010.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2010

Electrical Properties of Ba_0.5Sr_0.5Ta₂O₆ Thin Film Fabricated by Sol-Gel Method.

Li Lu, Masahiro Echizen, Takashi Nishida, Kiyoshi Uchiyama, Yukiharu Uraoka

IEICE Trans. Electron., 2010

1995

An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture.

Takeshi Sakata, Masashi Horiguchi, Tomonori Sekiguchi, Shigeki Ueda, Hitoshi Tanaka, Eiji Yamasaki, Yoshinobu Nakagome, Masakazu Aoki, Toru Kaga, Makoto Ohkura, Ryo Nagai, Fumio Murai, Toshihiko Tanaka, Shimpei Iijima, Natsuki Yokoyama, Yasushi Gotoh, Ken'ichi Shoji, Teruaki Kisu, Hisaomi Yamashita, Takashi Nishida, Eiji Takeda

IEEE J. Solid State Circuits, November, 1995

A 300-MHz 4-Mb wave-pipeline CMOS SRAM using a multiphase PLL.

Koichiro Ishibashi, Kunihiro Komiyaji, Hiroshi Toyoshima, Masataka Minami, Nagatoshi Ohki, Hiroshi Ishida, Toshiaki Yamanaka, Takahiro Nagano, Takashi Nishida

IEEE J. Solid State Circuits, November, 1995

A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers.

Koichiro Ishibashi, Koichi Takasugi, Kunihiro Komiyaji, Hiroshi Toyoshima, Toshiaki Yamanaka, Akira Fukami, Naotaka Hashimoto, Nagatoshi Ohki, Akihiro Shimizu, Takashi Hashimoto, Takahiro Nagano, Takashi Nishida

IEEE J. Solid State Circuits, April, 1995

1994

Hearing aid evaluation using variable - speech - rate audiometry.

Hiroshi Hosoi, Yoshiaki Tsuta, Takashi Nishida, Kiyotaka Murata, Fumihiko Ohta, Tsuyoshi Mekata, Yumiko Kato

Proceedings of the 3rd International Conference on Spoken Language Processing, 1994

1993

256-Mb DRAM circuit technologies for file applications.

Goro Kitsukawa, Masashi Horiguchi, Yoshiki Kawajiri, Takayuki Kawahara, Takesada Akiba, Yasushi Kawase, Toshikazu Tachibana, Takeshi Sakai, Masakazu Aoki, Syoji Shukuri, Kazuhiko Sagara, Ryo Nagai, Yuzuru Ohji, Nono Hasegawa, Natsuki Yokoyama, Teruaki Kisu, Hisaomi Yamashita, Tokuo Kure, Takashi Nishida

IEEE J. Solid State Circuits, November, 1993

1992

A 1.5-V full-swing BiCMOS logic circuit.

Mitsuru Hiraki, Kazuo Yano, Masataka Minami, Kazushige Sato, Nozomu Matsuzaki, Atsuo Watanabe, Takashi Nishida, Katsuro Sasaki, Koichi Seki

IEEE J. Solid State Circuits, November, 1992

3.3-V BiCMOS circuit techniques for 250-MHz RISC arithmetic modules.

Kazuo Yano, Mitsuru Hiraki, Shoji Shukuri, M. Hanawa, Masato Suzuki, S. Morita, A. Kawamata, Nagatoshi Ohki, Takashi Nishida, Koichi Seki

IEEE J. Solid State Circuits, March, 1992

1991

Quasi-complementary BiCMOS for sub-3-V digital circuits.

Kazuo Yano, Mitsuru Hiraki, Shoji Shukuri, Yasuo Onose, Mitsuru Hirao, Nagatoshi Ohki, Takashi Nishida, Koichi Seki, Katsuhiro Shimohigashi

IEEE J. Solid State Circuits, November, 1991

A block-oriented RAM with half-sized DRAM cell and quasi-folded data-line architecture.

Katsutaka Kimura, Takeshi Sakata, Kiyoo Itoh, Toru Kaga, Takashi Nishida, Yoshifumi Kawamoto

IEEE J. Solid State Circuits, November, 1991

Circuit techniques for 1.5-3.6-V battery-operated 64-Mb DRAM.

Yoshinobu Nakagome, Kiyoo Itoh, Kan Takeuchi, Eiji Kume, Hitoshi Tanaka, Masanori Isoda, Tatsunori Musha, Toru Kaga, Teruaki Kisu, Takashi Nishida, Yoshifumi Kawamoto, Masakazu Aoki

IEEE J. Solid State Circuits, July, 1991

An experimental 1.5-V 64-Mb DRAM.

Yoshinobu Nakagome, Hitoshi Tanaka, Kan Takeuchi, Eiji Kume, Yasushi Watanabe, Toru Kaga, Yoshifumi Kawamoto, Fumio Murai, Ryuichi Izawa, Digh Hisamoto, Teruaki Kisu, Takashi Nishida, Eiji Takeda, Kiyoo Itoh

IEEE J. Solid State Circuits, April, 1991

On-Chip Multiple Superscalar Processors with Secondary Cache Memories.

M. Hanawa, Tadahiko Nishimukai, O. Nishii, Masato Suzuki, Kazuo Yano, Mitsuru Hiraki, Shoji Shukuri, Takashi Nishida

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

1990

A 3.8-ns CMOS 16*16-b multiplier using complementary pass-transistor logic.

Kazuo Yano, Toshiaki Yamanaka, Takashi Nishida, Masayoshi Saito, Katsuhiro Shimohigashi, Akihiro Shimizu

IEEE J. Solid State Circuits, April, 1990

1989

A 9-ns 1-Mbit CMOS SRAM.

Katsuro Sasaki, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Takashi Nishida, Katsuhiro Shimohigashi, Shoji Hanamura, Shigeru Honjo

IEEE J. Solid State Circuits, October, 1989