Wenji Fang

Orcid: 0000-0002-8380-9395

According to our database1, Wenji Fang authored at least 24 papers between 2023 and 2025.

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Bibliography

2025
ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis.
CoRR, August, 2025

RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2025

GenEDA: Unleashing Generative Reasoning on Netlist via Multimodal Encoder-Decoder Aligned Foundation Model.
CoRR, April, 2025

NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph.
CoRR, April, 2025

A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA.
CoRR, April, 2025

OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation.
CoRR, March, 2025

Transferable Presynthesis PPA Estimation for RTL Designs With Data Augmentation Techniques.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2025

Profile-Guided Temporal Prefetching.
Proceedings of the 52nd Annual International Symposium on Computer Architecture, 2025

CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design.
Proceedings of the Thirteenth International Conference on Learning Representations, 2025

Towards Big Data in AI for EDA Research: Generation of New Pseudo Circuits at RTL Stage.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design Tasks.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024
TTNN: A Physically Guided Deep Learning Model for Focal Depth and Epicenter Distance Estimation Based on Multistation Waveforms.
IEEE Trans. Geosci. Remote. Sens., 2024

The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models.
CoRR, 2024

AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs.
CoRR, 2024

SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model.
CoRR, 2024

Erratum to: Large circuit models: opportunities and challenges.
Sci. China Inf. Sci., 2024

Large circuit models: opportunities and challenges.
Sci. China Inf. Sci., 2024

OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation.
Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023
r-map: Relating Implementation and Specification in Hardware Refinement Checking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution.
CoRR, 2023

WASIM: A Word-level Abstract Symbolic Simulation Framework for Hardware Formal Verification.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2023

MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023


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