Wenping Wang

Affiliations:
  • Vitesse Semiconductor, Austin, TX, USA
  • Arizona State University, Department of Electrical Engineering, Tempe, AZ, USA (PhD 2008)
  • Peking University, Microelectronics Department, Beijing, China (former)


According to our database1, Wenping Wang authored at least 20 papers between 2005 and 2013.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2013
NBTI-aware circuit node criticality computation.
ACM J. Emerg. Technol. Comput. Syst., 2013

2011
Leakage Power and Circuit Aging Cooptimization by Gate Replacement Techniques.
IEEE Trans. Very Large Scale Integr. Syst., 2011

2010
The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2010

2009
<i>New-Age</i>: A Negative Bias Temperature Instability-Estimation Framework for Microarchitectural Components.
Int. J. Parallel Program., 2009

The Predictive Technology Model in the Late Silicon Era and Beyond.
Found. Trends Electron. Des. Autom., 2009

On the efficacy of input Vector Control to mitigate NBTI effects and leakage power.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Gate replacement techniques for simultaneous leakage and aging optimization.
Proceedings of the Design, Automation and Test in Europe, 2009

A framework for estimating NBTI degradation of microarchitectural components.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Case Study of Reliability-Aware and Low-Power Design.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Scalable model for predicting the effect of negative bias temperature instability for reliable design.
IET Circuits Devices Syst., 2008

Optimized Circuit Failure Prediction for Aging: Practicality and Promise.
Proceedings of the 2008 IEEE International Test Conference, 2008

Node Criticality Computation for Circuit Timing Analysis and Optimization under NBTI Effect.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Statistical prediction of circuit aging under process variations.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
An efficient method to identify critical gates under circuit aging.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

The Impact of NBTI on the Performance of Combinational and Sequential Circuits.
Proceedings of the 44th Design Automation Conference, 2007

An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS Technology.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
Modeling and minimization of PMOS NBTI effect for robust nanometer design.
Proceedings of the 43rd Design Automation Conference, 2006

Predictive Modeling of the NBTI Effect for Reliable Design.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Low-leakage robust SRAM cell design for sub-100nm technologies.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005


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