William P. Risk
According to our database1,
William P. Risk
authored at least 12 papers
between 2012 and 2024.
Collaborative distances:
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Bibliography
2024
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
Proceedings of the 35th IEEE Hot Chips Symposium, 2023
2019
2016
Truenorth ecosystem for brain-inspired computing: scalable systems, software, and applications.
Proceedings of the International Conference for High Performance Computing, 2016
2015
TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
2014
Real-Time Scalable Cortical Computing at 46 Giga-Synaptic OPS/Watt with ~100× Speedup in Time-to-Solution and ~100, 000× Reduction in Energy-to-Solution.
Proceedings of the International Conference for High Performance Computing, 2014
2013
Cognitive computing systems: Algorithms and applications for networks of neurosynaptic cores.
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013
Cognitive computing building block: A versatile and efficient digital neuron model for neurosynaptic cores.
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013
Cognitive computing programming paradigm: A Corelet Language for composing networks of neurosynaptic cores.
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013
2012
Proceedings of the SC Conference on High Performance Computing Networking, 2012
Building block of a programmable neuromorphic substrate: A digital neurosynaptic core.
Proceedings of the 2012 International Joint Conference on Neural Networks (IJCNN), 2012