Steven K. Esser
Affiliations:- IBM Research, Almaden Research Center, San Jose, USA
According to our database1,
Steven K. Esser
authored at least 25 papers
between 2009 and 2024.
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Bibliography
2024
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
Efficient and Effective Methods for Mixed Precision Neural Network Quantization for Faster, Energy-efficient Inference.
CoRR, 2023
Proceedings of the 35th IEEE Hot Chips Symposium, 2023
2020
Proceedings of the 8th International Conference on Learning Representations, 2020
2019
Discovering Low-Precision Networks Close to Full-Precision Networks for Efficient Inference.
Proceedings of the Fifth Workshop on Energy Efficient Machine Learning and Cognitive Computing, 2019
2018
Low Precision Policy Distillation with Application to Low-Power, Real-time Sensation-Cognition-Action Loop with Neuromorphic Computing.
CoRR, 2018
Discovering Low-Precision Networks Close to Full-Precision Networks for Efficient Embedded Inference.
CoRR, 2018
2017
Proceedings of the 2017 IEEE Conference on Computer Vision and Pattern Recognition, 2017
2016
Proc. Natl. Acad. Sci. USA, 2016
Deep neural networks are robust to weight binarization and other non-linear distortions.
CoRR, 2016
Truenorth ecosystem for brain-inspired computing: scalable systems, software, and applications.
Proceedings of the International Conference for High Performance Computing, 2016
2015
Proceedings of the Advances in Neural Information Processing Systems 28: Annual Conference on Neural Information Processing Systems 2015, 2015
2014
Real-Time Scalable Cortical Computing at 46 Giga-Synaptic OPS/Watt with ~100× Speedup in Time-to-Solution and ~100, 000× Reduction in Energy-to-Solution.
Proceedings of the International Conference for High Performance Computing, 2014
2013
Cognitive computing systems: Algorithms and applications for networks of neurosynaptic cores.
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013
Cognitive computing building block: A versatile and efficient digital neuron model for neurosynaptic cores.
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013
Cognitive computing programming paradigm: A Corelet Language for composing networks of neurosynaptic cores.
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013
2012
Proceedings of the SC Conference on High Performance Computing Networking, 2012
Building block of a programmable neuromorphic substrate: A digital neurosynaptic core.
Proceedings of the 2012 International Joint Conference on Neural Networks (IJCNN), 2012
2011
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
2010
Proceedings of the International Joint Conference on Neural Networks, 2010
2009
The cat is out of the bag: cortical simulations with 10<sup>9</sup> neurons, 10<sup>13</sup> synapses.
Proceedings of the ACM/IEEE Conference on High Performance Computing, 2009