Michael P. Beakes

According to our database, Michael P. Beakes authored at least 25 papers between 2001 and 2023.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2023

A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links.

Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, Troy J. Beukema, Marcel A. Kossel, Thomas Morf, Young-Ho Choi, Pier Andrea Francese, Matthias Brändli, Christian W. Baks, Jonathan E. Proesel, John F. Bulzacchelli, Michael P. Beakes, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo-Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin

IEEE J. Solid State Circuits, 2023

2022

An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS.

Serdar S. Yonar, Pier Andrea Francese, Matthias Brändli, Marcel A. Kossel, Thomas Morf, Jonathan E. Proesel, Sergey V. Rylov, Herschel A. Ainspan, Martin Cochet, Zeynep Toprak Deniz, Timothy O. Dickson, Troy J. Beukema, Christian W. Baks, Michael P. Beakes, John F. Bulzacchelli, Young-Ho Choi, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo-Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links.

Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, Marcel A. Kossel, Thomas Morf, Young-Ho Choi, Pier Andrea Francese, Matthias Brändli, Troy J. Beukema, Christian W. Baks, Jonathan E. Proesel, John F. Bulzacchelli, Michael P. Beakes, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo-Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2020

Errata Erratum to "A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS".

Zeynep Toprak Deniz, Jonathan E. Proesel, John F. Bulzacchelli, Herschel A. Ainspan, Timothy O. Dickson, Michael P. Beakes, Mounir Meghelli

IEEE J. Solid State Circuits, 2020

A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS.

Zeynep Toprak Deniz, Jonathan E. Proesel, John F. Bulzacchelli, Herschel A. Ainspan, Timothy O. Dickson, Michael P. Beakes, Mounir Meghelli

IEEE J. Solid State Circuits, 2020

2019

Multi-Wavelength Optical Transceivers Integrated on Node (MOTION).

Daniel M. Kuchta, Jonathan E. Proesel, Fuad E. Doany, Wooram Lee, Timothy O. Dickson, Herschel A. Ainspan, Mounir Meghelli, Petar K. Pepeljugoski, Xiaoxiong Gu, Michael P. Beakes, Mark Schultz, Marc Taubenblatt, Paul Fortier, Catherine Dufort, Éric Turcotte, Marc-Olivier Pion, Charles Bureau, Frank Flens, Greta Light, Blake Trekell, Kevin Koski

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2019

A 128Gb/s 1.3pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOS.

Zeynep Toprak Deniz, Jonathan E. Proesel, John F. Bulzacchelli, Herschel A. Ainspan, Timothy O. Dickson, Michael P. Beakes, Mounir Meghelli

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2016

A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration.

Timothy O. Dickson, Yong Liu, Ankur Agrawal, John F. Bulzacchelli, Herschel A. Ainspan, Zeynep Toprak Deniz, Benjamin D. Parker, Michael P. Beakes, Mounir Meghelli, Daniel J. Friedman

IEEE J. Solid State Circuits, 2016

3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI.

Sergey V. Rylov, Troy J. Beukema, Zeynep Toprak Deniz, Thomas Toifl, Yong Liu, Ankur Agrawal, Peter Buchmann, Alexander V. Rylyakov, Michael P. Beakes, Benjamin D. Parker, Mounir Meghelli

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015

TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip.

Filipp Akopyan, Jun Sawada, Andrew Cassidy, Rodrigo Alvarez-Icaza, John V. Arthur, Paul Merolla, Nabil Imam, Yutaka Y. Nakamura, Pallab Datta, Gi-Joon Nam, Brian Taba, Michael P. Beakes, Bernard Brezzo, Jente B. Kuang, Rajit Manohar, William P. Risk, Bryan L. Jackson, Dharmendra S. Modha

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic Switch Networks.

Alexander V. Rylyakov, Jonathan E. Proesel, Sergey V. Rylov, Benjamin G. Lee, John F. Bulzacchelli, Abhijeet Ardey, Benjamin D. Parker, Michael P. Beakes, Christian W. Baks, Clint Schow, Mounir Meghelli

IEEE J. Solid State Circuits, 2015

A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology.

Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark A. Ferriss, Herschel A. Ainspan, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Christian W. Baks, Lei Shan, Young Hoon Kwark, José A. Tierno, Daniel J. Friedman

IEEE J. Solid State Circuits, 2015

22.1 A 25Gb/s burst-mode receiver for rapidly reconfigurable optical networks.

Alexander V. Rylyakov, Jonathan E. Proesel, Sergey V. Rylov, Benjamin G. Lee, John F. Bulzacchelli, Abhijeet Ardey, Benjamin D. Parker, Michael P. Beakes, Christian W. Baks, Clint Schow, Mounir Meghelli

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014

A 3.5pJ/bit 8-tap-feed-forward 8-tap-decision feedback digital equalizer for 16Gb/s I/Os.

Thomas Toifl, Peter Buchmann, Troy J. Beukema, Michael P. Beakes, Matthias Braendli, Pier Andrea Francese, Christian Menolfi, Marcel A. Kossel, Lukas Kull, Thomas Morf

Proceedings of the ESSCIRC 2014, 2014

2013

A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS.

Jean-Olivier Plouchart, Mark A. Ferriss, A. S. Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Aydin Babakhani, Soner Yaldiz, Larry T. Pileggi, Ramesh Harjani, Scott K. Reynolds, José A. Tierno, Daniel J. Friedman

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

2012

An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects.

Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Bing Dang, Cornelia K. Tsang, Paul S. Andry, John F. Bulzacchelli, Herschel A. Ainspan, Xiaoxiong Gu, Lavanya Turlapati, Michael P. Beakes, Benjamin D. Parker, John U. Knickerbocker, Daniel J. Friedman

IEEE J. Solid State Circuits, 2012

A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS.

Jean-Olivier Plouchart, Mihai A. T. Sanduleanu, Zeynep Toprak Deniz, Troy J. Beukema, Scott K. Reynolds, Benjamin D. Parker, Michael P. Beakes, José A. Tierno, Daniel J. Friedman

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS.

Jean-Olivier Plouchart, Mark A. Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Aydin Babakhani, Soner Yaldiz, Lawrence T. Pileggi, Ramesh Harjani, Scott K. Reynolds, José A. Tierno, Daniel J. Friedman

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2009

A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS.

John F. Bulzacchelli, Timothy O. Dickson, Zeynep Toprak Deniz, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes, Sergey V. Rylov, Daniel J. Friedman

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2007

A 7Gb/s 9.3mW 2-Tap Current-Integrating DFE Receiver.

Matt Park, John F. Bulzacchelli, Michael P. Beakes, Daniel J. Friedman

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006

A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology.

John F. Bulzacchelli, Mounir Meghelli, Sergey V. Rylov, Woogeun Rhee, Alexander V. Rylyakov, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes, Aichin Chung, Troy J. Beukema, Petar K. Pepeljugoski, Lei Shan, Young Hoon Kwark, Sudhir M. Gowda, Daniel J. Friedman

IEEE J. Solid State Circuits, 2006

A 10Gb/s 5-Tap-DFE/4-Tap-FFE Transceiver in 90nm CMOS.

Mounir Meghelli, Sergey V. Rylov, John F. Bulzacchelli, Woogeun Rhee, Alexander V. Rylyakov, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes, Aichin Chung, Troy J. Beukema, Petar K. Pepeljugoski, L. Shan, Young Hoon Kwark, Sudhir M. Gowda, Daniel J. Friedman

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005

A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization.

Troy J. Beukema, Michael Sorna, Karl Selander, Steven Zier, Brian L. Ji, Phil Murfet, James Mason, Woogeun Rhee, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes

IEEE J. Solid State Circuits, 2005

2003

A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop.

Woogeun Rhee, Herschel A. Ainspan, Sergey V. Rylov, Alexander V. Rylyakov, Michael P. Beakes, Daniel J. Friedman, Sudhir M. Gowda, Mehmet Soyuer

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2001

Single-chip 622-Mb/s SDH/SONET framer, digital cross-connect and add/drop multiplexer solution.

Peter H. Baechtold, Michael P. Beakes, Peter Buchmann, Rolf Clauberg, John F. Ewen, John F. Gilsdorf, Philippe Hauviller, Andreas Herkersdorf, Jean-Claude Le Garrec, Wolfram W. Lemppenau, Ben Parker, Dale J. Pearson, Joseph M. Pereira, Dominique Plassat, Scott K. Reynolds, Hans R. Schindler, André Steimle, David J. Webb, Albert X. Widmer

IEEE J. Solid State Circuits, 2001