Michael P. Beakes

According to our database1, Michael P. Beakes authored at least 18 papers between 2006 and 2020.

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Bibliography

2020
Errata Erratum to "A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS".
IEEE J. Solid State Circuits, 2020

A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS.
IEEE J. Solid State Circuits, 2020

2019

A 128Gb/s 1.3pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2016
A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration.
IEEE J. Solid State Circuits, 2016

3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic Switch Networks.
IEEE J. Solid State Circuits, 2015

A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology.
IEEE J. Solid State Circuits, 2015

22.1 A 25Gb/s burst-mode receiver for rapidly reconfigurable optical networks.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
A 3.5pJ/bit 8-tap-feed-forward 8-tap-decision feedback digital equalizer for 16Gb/s I/Os.
Proceedings of the ESSCIRC 2014, 2014

2013
A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

2012
An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects.
IEEE J. Solid State Circuits, 2012

A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012


2009
A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2007
A 7Gb/s 9.3mW 2-Tap Current-Integrating DFE Receiver.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
A 10Gb/s 5-Tap-DFE/4-Tap-FFE Transceiver in 90nm CMOS.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006


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