Rajit Manohar

According to our database1, Rajit Manohar authored at least 91 papers between 1995 and 2019.

Collaborative distances:
  • Dijkstra number2 of two.
  • Erdős number3 of three.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Homepages:

On csauthors.net:

Bibliography

2019
Operation-Dependent Frequency Scaling Using Desynchronization.
IEEE Trans. VLSI Syst., 2019

Self-Timed Adaptive Digit-Serial Addition.
IEEE Trans. VLSI Syst., 2019

QDI Constant-Time Counters.
IEEE Trans. VLSI Syst., 2019

Braindrop: A Mixed-Signal Neuromorphic Architecture With a Dynamical Systems-Based Programming Model.
Proceedings of the IEEE, 2019

SPRoute: A Scalable Parallel Negotiation-based Global Router.
Proceedings of the International Conference on Computer-Aided Design, 2019

Asynchronous Signalling Processes.
Proceedings of the 25th IEEE International Symposium on Asynchronous Circuits and Systems, 2019

AMC: An Asynchronous Memory Compiler.
Proceedings of the 25th IEEE International Symposium on Asynchronous Circuits and Systems, 2019

2018
Exact Timing Analysis for Asynchronous Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

A Continuous-Time Digital IIR Filter With Signal-Derived Timing and Fully Agile Power Consumption.
J. Solid-State Circuits, 2018

The Impact of On-chip Communication on Memory Technologies for Neuromorphic Systems.
CoRR, 2018

2017
Energy-efficient hybrid CMOS-NEMS LIF neuron circuit in 28 nm CMOS process.
Proceedings of the 2017 IEEE Symposium Series on Computational Intelligence, 2017

On Using Time Without Clocks via Zigzag Causality.
Proceedings of the ACM Symposium on Principles of Distributed Computing, 2017

Toolbox for exploration of energy-efficient event processors for human-computer interaction.
Proceedings of the 2017 IEEE International Symposium on Performance Analysis of Systems and Software, 2017

DeepRecon: Dynamically reconfigurable architecture for accelerating deep neural networks.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

Accelerating Face Detection on Programmable SoC Using C-Based Synthesis.
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

Design of tunable digital delay cells.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

The Eventual C-Element Theorem for Delay-Insensitive Asynchronous Circuits.
Proceedings of the 23rd IEEE International Symposium on Asynchronous Circuits and Systems, 2017

2016
Gradual Synchronization.
Proceedings of the 22nd IEEE International Symposium on Asynchronous Circuits and Systems, 2016

2015
TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Comparing Stochastic and Deterministic Computing.
Computer Architecture Letters, 2015

Preventing glitches and short circuits in high-level self-timed chip specifications.
Proceedings of the 36th ACM SIGPLAN Conference on Programming Language Design and Implementation, 2015

Design of a QDI asynchronous AER serializer/deserializer link in 180nm for event-based sensors for robotic applications.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Automatic obfuscated cell layout for trusted split-foundry design.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015

AES Hardware-Software Co-design in WSN.
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

Analyzing Isochronic Forks with Potential Causality.
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

Timing Driven Placement for Quasi Delay-Insensitive Circuits.
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

2014
An asymmetric dual-processor architecture for low-power information appliances.
ACM Trans. Embedded Comput. Syst., 2014


ULSNAP: An ultra-low power event-driven microcontroller for sensor network nodes.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Removing concurrency for rapid functional verification.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Using asymmetric cores to reduce power consumption for interactive devices with bi-stable displays.
Proceedings of the CHI Conference on Human Factors in Computing Systems, 2014

Low Power Asynchronous VLSI with NEM Relays.
Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems, 2014

2013
Neural spiking dynamics in asynchronous digital circuits.
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013

A memory-efficient routing method for large-scale spiking neural networks.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

A split-foundry asynchronous FPGA.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

A Bit of Analysis on Self-Timed Single-Bit On-Chip Links.
Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems, 2013

Inverting Martin Synthesis for Verification.
Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems, 2013

cellTK: Automated Layout for Asynchronous Circuits with Nonstandard Cells.
Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems, 2013

2012
Dynamic electrothermal simulation of three-dimensional integrated circuits using standard cell macromodels.
IET Circuits, Devices & Systems, 2012

Building block of a programmable neuromorphic substrate: A digital neurosynaptic core.
Proceedings of the 2012 International Joint Conference on Neural Networks (IJCNN), 2012

A Low Power Asynchronous GPS Baseband Processor.
Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012

An Asynchronous Floating-Point Multiplier.
Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012

A Digital Neurosynaptic Core Using Event-Driven QDI Circuits.
Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012

2011
Energy-Efficient Pipeline Templates for High-Performance Asynchronous Circuits.
JETC, 2011

A digital neurosynaptic core using embedded crossbar memory with 45pJ per spike in 45nm.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

Address-Event Communication Using Token-Ring Mutual Exclusion.
Proceedings of the 17th IEEE International Symposium on Asynchronous Circuits and Systems, 2011

2010
An Operand-Optimized Asynchronous IEEE 754 Double-Precision Floating-Point Adder.
Proceedings of the 16th IEEE International Symposium on Asynchronous Circuits and Systems, 2010

Static Power Reduction Techniques for Asynchronous Circuits.
Proceedings of the 16th IEEE International Symposium on Asynchronous Circuits and Systems, 2010

An Asynchronous FPGA with Two-Phase Enable-Scaled Routing.
Proceedings of the 16th IEEE International Symposium on Asynchronous Circuits and Systems, 2010

2009
Reducing Power Consumption with Relaxed Quasi Delay-Insensitive Circuits.
Proceedings of the 15th IEEE Symposium on Asynchronous Circuits and Systems, 2009

2008
Variability in 3-D integrated circuits.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
Analog and asynchronous variation-aware circuits.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor.
Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2007

2006
Self-Timed Thermally-Aware Circuits.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Yield enhancement of asynchronous logic circuits through 3-dimensional integration technology.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Reconfigurable Asynchronous Logic.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

Self-Healing Asynchronous Arrays.
Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 2006

A Level-Crossing Flash Asynchronous Analog-to-Digital Converter.
Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 2006

2005
Mapping system-on-chip designs from 2-D to 3-D ICs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Fault Tolerant Asynchronous Adder through Dynamic Self-reconfiguration.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Automated synthesis for asynchronous FPGAs.
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

A High-Performance Asynchronous FPGA: Test Results.
Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005

Efficient Failure Detection in Pipelined Asynchronous Circuits.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

BitSNAP: Dynamic Significance Compression for a Low-Energy Sensor Network Asynchronous Processor.
Proceedings of the 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 2005

2004
An Asynchronous Dataflow FPGA Architecture.
IEEE Trans. Computers, 2004

Highly pipelined asynchronous FPGAs.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

Fault Detection and Isolation Techniques for Quasi Delay-Insensitive Circuits.
Proceedings of the 2004 International Conference on Dependable Systems and Networks (DSN 2004), 28 June, 2004

Static Tokens: Using Dataflow to Automate Concurrent Pipeline Synthesis.
Proceedings of the 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 2004

Non-Uniform Access Asynchronous Register Files.
Proceedings of the 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 2004

An ultra low-power processor for sensor networks.
Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems, 2004

2003
Power optimal routing in wireless networks.
Proceedings of IEEE International Conference on Communications, 2003

Programmable Asynchronous Pipeline Arrays.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

An Event-Synchronization Protocol for Parallel Simulation of Large-Scale Wireless Networks.
Proceedings of the 7th IEEE International Symposium on Distributed Simulation and Real-Time Applications (DS-RT 2003), 2003

A High-Speed Clockless Serial Link Transceiver.
Proceedings of the 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 2003

SNAP: A Sensor-Network Asynchronous Processor.
Proceedings of the 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 2003

Asynchronous DRAM Design and Synthesis.
Proceedings of the 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 2003

2002
Scalable formal design methods for asynchronous VLSI.
Proceedings of the Conference Record of POPL 2002: The 29th SIGPLAN-SIGACT Symposium on Principles of Programming Languages, 2002

Energy-Efficient Pipelines.
Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002

2001
An Analysis of Reshuffled Handshaking Expansions.
Proceedings of the 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 2001

Precise Exceptions in Asynchronous Processors.
Proceedings of the 19th Conference on Advanced Research in VLSI (ARVLSI 2001), 2001

Width-Adaptive Data Word Architectures.
Proceedings of the 19th Conference on Advanced Research in VLSI (ARVLSI 2001), 2001

1999
The entropy of traces in parallel computation.
IEEE Trans. Information Theory, 1999

Joining Specification Statements.
Theor. Comput. Sci., 1999

Projection: A Synthesis Technique for Concurrent Systems.
Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 1999

1998
Asynchronous Parallel Prefix Computation.
IEEE Trans. Computers, 1998

Slack Elasticity in Concurrent Computing.
Proceedings of the Mathematics of Program Construction, 1998

1997
Performance and Portability of an Air Quality Model.
Parallel Comput., 1997

The Design of an Asynchronous MIPS R3000 Microprocessor.
Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97), 1997

1996
The energy and entropy of VLSI computations.
Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '96), 1996

1995
Conditional Composition.
Formal Asp. Comput., 1995

Integrating task and data parallelism with the group communication archetype.
Proceedings of IPPS '95, 1995


  Loading...