Brian Van Essen

Orcid: 0000-0002-2281-7500

Affiliations:
  • Lawrence Livermore National Laboratory, CA, USA


According to our database1, Brian Van Essen authored at least 44 papers between 2006 and 2022.

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Bibliography

2022
Enabling machine learning-ready HPC ensembles with Merlin.
Future Gener. Comput. Syst., 2022

Scalable Composition and Analysis Techniques for Massive Scientific Workflows.
Proceedings of the 18th IEEE International Conference on e-Science, 2022

Parallelizing Graph Neural Networks via Matrix Compaction for Edge-Conditioned Networks.
Proceedings of the 22nd IEEE International Symposium on Cluster, 2022

2021
The Case for Strong Scaling in Deep Learning: Training Large 3D CNNs With Hybrid Parallelism.
IEEE Trans. Parallel Distributed Syst., 2021

Machine-learning-based dynamic-importance sampling for adaptive multiscale simulations.
Nat. Mach. Intell., 2021

Enabling rapid COVID-19 small molecule drug design through scalable deep learning of generative models.
Int. J. High Perform. Comput. Appl., 2021

Co-design Center for Exascale Machine Learning Technologies (ExaLearn).
Int. J. High Perform. Comput. Appl., 2021

Is Disaggregation possible for HPC Cognitive Simulation?
Proceedings of the IEEE/ACM Workshop on Machine Learning in High Performance Computing Environments, 2021

SUPER: SUb-Graph Parallelism for TransformERs.
Proceedings of the 35th IEEE International Parallel and Distributed Processing Symposium, 2021

Monitoring Large Scale Supercomputers: A Case Study with the Lassen Supercomputer.
Proceedings of the IEEE International Conference on Cluster Computing, 2021

2020
Scalable Topological Data Analysis and Visualization for Evaluating Data-Driven Models in Scientific Applications.
IEEE Trans. Vis. Comput. Graph., 2020

2019
Merlin: Enabling Machine Learning-Ready HPC Ensembles.
CoRR, 2019

Distinguishing between Normal and Cancer Cells Using Autoencoder Node Saliency.
CoRR, 2019


Channel and filter parallelism for large-scale CNN training.
Proceedings of the International Conference for High Performance Computing, 2019

Improving Strong-Scaling of CNN Training by Exploiting Finer-Grained Parallelism.
Proceedings of the 2019 IEEE International Parallel and Distributed Processing Symposium, 2019

Parallelizing Training of Deep Generative Models on Massive Scientific Datasets.
Proceedings of the 2019 IEEE International Conference on Cluster Computing, 2019

Proceedings of the Operating Systems for Supercomputers and High Performance Computing, 2019

2018
Modular Spiking Neural Circuits for Mapping Long Short-Term Memory on a Neurosynaptic Processor.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

The History Began from AlexNet: A Comprehensive Survey on Deep Learning Approaches.
CoRR, 2018

CANDLE/Supervisor: a workflow framework for machine learning applied to cancer research.
BMC Bioinform., 2018

Effective Quantization Approaches for Recurrent Neural Networks.
Proceedings of the 2018 International Joint Conference on Neural Networks, 2018

2017
Towards Scalable Parallel Training of Deep Neural Networks.
Proceedings of the Machine Learning on HPC Environments, 2017

Argo NodeOS: Toward Unified Resource Management for Exascale.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium, 2017

Quadratic Unconstrained Binary Optimization (QUBO) on neuromorphic computing system.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

Convolutional sparse coding on neurosynaptic cognitive system.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

A spike-based long short-term memory on a neurosynaptic processor.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

2016

Communication Quantization for Data-Parallel Training of Deep Neural Networks.
Proceedings of the 2nd Workshop on Machine Learning in HPC Environments, 2016

Towards a Distributed Large-Scale Dynamic Graph Data Store.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

2015
Large-Scale Deep Learning on the YFCC100M Dataset.
CoRR, 2015

DI-MMAP - a scalable memory-map runtime for out-of-core data-intensive applications.
Clust. Comput., 2015

LBANN: livermore big artificial neural network HPC toolkit.
Proceedings of the Workshop on Machine Learning in High-Performance Computing Environments, 2015

A Container-Based Approach to OS Specialization for Exascale Computing.
Proceedings of the 2015 IEEE International Conference on Cloud Engineering, 2015

2014
Multi-threaded streamline tracing for data-intensive architectures.
Proceedings of the 4th IEEE Symposium on Large Data Analysis and Visualization, 2014

2012
DI-MMAP: A High Performance Memory-Map Runtime for Data-Intensive Applications.
Proceedings of the 2012 SC Companion: High Performance Computing, 2012

On the Role of NVRAM in Data-intensive Architectures: An Evaluation.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium, 2012

Integrated in-system storage architecture for high performance computing.
Proceedings of the 2nd International Workshop on Runtime and Operating Systems for Supercomputers, 2012

Accelerating a Random Forest Classifier: Multi-Core, GP-GPU, or FPGA?
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

2011
Energy-efficient specialization of functional units in a coarse-grained reconfigurable array.
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

2010
Managing Short-Lived and Long-Lived Values in Coarse-Grained Reconfigurable Arrays.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

2009
Static versus scheduled interconnect in Coarse-Grained Reconfigurable Arrays.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

SPR: an architecture-adaptive CGRA mapping tool.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

2006
A type architecture for hybrid micro-parallel computers.
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006


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