Andrew S. Cassidy

According to our database1, Andrew S. Cassidy authored at least 33 papers between 2002 and 2019.

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Bibliography

2019
TrueNorth: Accelerating From Zero to 64 Million Neurons in 10 Years.
Computer, 2019

2018
Spiking Optical Flow for Event-Based Sensors Using IBM's TrueNorth Neurosynaptic System.
IEEE Trans. Biomed. Circuits Syst., 2018

Word2vec Word Similarities on IBM's TrueNorth Neurosynaptic System.
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018

2017
Always-On Speech Recognition Using TrueNorth, a Reconfigurable, Neurosynaptic Processor.
IEEE Trans. Computers, 2017

2016
Convolutional networks for fast, energy-efficient neuromorphic computing.
Proc. Natl. Acad. Sci. USA, 2016


Real-time sensory information processing using the TrueNorth Neurosynaptic System.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

LATTE: Low-power Audio Transform with TrueNorth Ecosystem.
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016

TrueHappiness: Neuromorphic emotion recognition on TrueNorth.
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016

A low-power neurosynaptic implementation of Local Binary Patterns for texture analysis.
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016

Conversion of artificial recurrent neural networks to spiking neural networks for low-power neuromorphic hardware.
Proceedings of the IEEE International Conference on Rebooting Computing, 2016

2015
TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Visual saliency on networks of neurosynaptic cores.
IBM J. Res. Dev., 2015

Gibbs sampling with low-power spiking digital neurons.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014

2013
Design of silicon brains in the nano-CMOS era: Spiking neurons, learning synapses and neural architecture optimization.
Neural Networks, 2013


Cognitive computing building block: A versatile and efficient digital neuron model for neurosynaptic cores.
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013

Cognitive computing programming paradigm: A Corelet Language for composing networks of neurosynaptic cores.
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013

2012
Beyond Amdahl's Law: An Objective Function That Links Multiprocessor Performance Gains to Delay and Energy.
IEEE Trans. Computers, 2012

Building block of a programmable neuromorphic substrate: A digital neurosynaptic core.
Proceedings of the 2012 International Joint Conference on Neural Networks (IJCNN), 2012

2011
Evaluating on-chip interconnects for low operating frequency silicon neuron arrays.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A combinational digital logic approach to STDP.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A high-level analytical model for application specific CMP design exploration.
Proceedings of the Design, Automation and Test in Europe, 2011

A wireless architecture for distributed sensing/actuation and pre-processing with microsecond synchronization.
Proceedings of the 45st Annual Conference on Information Sciences and Systems, 2011

A multimodal-corpus data collection system for cognitive acoustic scene analysis.
Proceedings of the 45st Annual Conference on Information Sciences and Systems, 2011

Design of a one million neuron single FPGA neuromorphic system for real-time multimodal scene analysis.
Proceedings of the 45st Annual Conference on Information Sciences and Systems, 2011

2009
A Switched Capacitor Implementation of the Generalized Linear Integrate-and-fire Neuron.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Analyzing features for automatic age estimation on cross-sectional data.
Proceedings of the INTERSPEECH 2009, 2009

Analytical methods for the design and optimization of chip-multiprocessor architectures.
Proceedings of the 43rd Annual Conference on Information Sciences and Systems, 2009

2005
High-level modeling and simulation of single-chip programmable heterogeneous multiprocessors.
ACM Trans. Design Autom. Electr. Syst., 2005

2003
Layered, Multi-Threaded, High-Level Performance Design.
Proceedings of the 2003 Design, 2003

2002
System-Level Modeling of a Network Switch SoC.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002


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