Andrew S. Cassidy
Orcid: 0000-0001-7305-4198
According to our database1,
Andrew S. Cassidy
authored at least 36 papers
between 2002 and 2024.
Collaborative distances:
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Bibliography
2024
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
Proceedings of the 35th IEEE Hot Chips Symposium, 2023
2019
2018
Spiking Optical Flow for Event-Based Sensors Using IBM's TrueNorth Neurosynaptic System.
IEEE Trans. Biomed. Circuits Syst., 2018
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018
2017
Always-On Speech Recognition Using TrueNorth, a Reconfigurable, Neurosynaptic Processor.
IEEE Trans. Computers, 2017
2016
Proc. Natl. Acad. Sci. USA, 2016
Truenorth ecosystem for brain-inspired computing: scalable systems, software, and applications.
Proceedings of the International Conference for High Performance Computing, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016
A low-power neurosynaptic implementation of Local Binary Patterns for texture analysis.
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016
Conversion of artificial recurrent neural networks to spiking neural networks for low-power neuromorphic hardware.
Proceedings of the IEEE International Conference on Rebooting Computing, 2016
2015
TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
Real-Time Scalable Cortical Computing at 46 Giga-Synaptic OPS/Watt with ~100× Speedup in Time-to-Solution and ~100, 000× Reduction in Energy-to-Solution.
Proceedings of the International Conference for High Performance Computing, 2014
2013
Design of silicon brains in the nano-CMOS era: Spiking neurons, learning synapses and neural architecture optimization.
Neural Networks, 2013
Cognitive computing systems: Algorithms and applications for networks of neurosynaptic cores.
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013
Cognitive computing building block: A versatile and efficient digital neuron model for neurosynaptic cores.
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013
Cognitive computing programming paradigm: A Corelet Language for composing networks of neurosynaptic cores.
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013
2012
Beyond Amdahl's Law: An Objective Function That Links Multiprocessor Performance Gains to Delay and Energy.
IEEE Trans. Computers, 2012
Building block of a programmable neuromorphic substrate: A digital neurosynaptic core.
Proceedings of the 2012 International Joint Conference on Neural Networks (IJCNN), 2012
2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the Design, Automation and Test in Europe, 2011
A wireless architecture for distributed sensing/actuation and pre-processing with microsecond synchronization.
Proceedings of the 45st Annual Conference on Information Sciences and Systems, 2011
Proceedings of the 45st Annual Conference on Information Sciences and Systems, 2011
Design of a one million neuron single FPGA neuromorphic system for real-time multimodal scene analysis.
Proceedings of the 45st Annual Conference on Information Sciences and Systems, 2011
2009
A Switched Capacitor Implementation of the Generalized Linear Integrate-and-fire Neuron.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the INTERSPEECH 2009, 2009
Analytical methods for the design and optimization of chip-multiprocessor architectures.
Proceedings of the 43rd Annual Conference on Information Sciences and Systems, 2009
2005
High-level modeling and simulation of single-chip programmable heterogeneous multiprocessors.
ACM Trans. Design Autom. Electr. Syst., 2005
2003
Proceedings of the 2003 Design, 2003
2002
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002