Xiangqu Fu

Orcid: 0000-0001-7288-9302

According to our database1, Xiangqu Fu authored at least 7 papers between 2023 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2025
A High-Density Energy-Efficient CNM Macro Using Hybrid RRAM and SRAM for Memory-Bound Applications.
IEEE Trans. Very Large Scale Integr. Syst., August, 2025

SHMT: An SRAM and HBM Hybrid Computing-in-Memory Architecture With Optimized KV Cache for Multimodal Transformer.
IEEE Trans. Circuits Syst. I Regul. Pap., June, 2025

2024
A Multichiplet Computing-in-Memory Architecture Exploration Framework Based on Various CIM Devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2024

A 28-nm Computing-in-Memory-Based Super-Resolution Accelerator Incorporating Macro-Level Pipeline and Texture/Algebraic Sparsity.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2024

IG-CRM: Area/Energy-Efficient IGZO-Based Circuits and Architecture Design for Reconfigurable CIM/CAM Applications.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023
P<sup>3</sup> ViT: A CIM-Based High-Utilization Architecture With Dynamic Pruning and Two-Way Ping-Pong Macro for Vision Transformer.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023

A Security-Enhanced, Charge-Pump-Free, ISO14443-A-/ISO10373-6-Compliant RFID Tag With 16.2-μW Embedded RRAM and Reconfigurable Strong PUF.
IEEE Trans. Very Large Scale Integr. Syst., February, 2023


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