Xiaoxuan Yang

Orcid: 0000-0002-2553-2631

Affiliations:
  • University of Virginia, Department of Electrical and Computer Engineering, Charlottesville, VA, USA
  • Stanford University, Stanford, CA, USA (former)
  • Duke University, Durham, NC, USA (former, PhD 2023)


According to our database1, Xiaoxuan Yang authored at least 19 papers between 2020 and 2025.

Collaborative distances:

Timeline

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Bibliography

2025
Optimizing and Exploring System Performance in Compact Processing-in-Memory-based Chips.
CoRR, February, 2025

AutoRAC: Automated Processing-in-Memory Accelerator Design for Recommender Systems.
Proceedings of the Great Lakes Symposium on VLSI 2025, GLSVLSI 2025, New Orleans, LA, USA, 30 June 2025, 2025

Titanus: Enabling KV Cache Pruning and Quantization On-the-Fly for LLM Acceleration.
Proceedings of the Great Lakes Symposium on VLSI 2025, GLSVLSI 2025, New Orleans, LA, USA, 30 June 2025, 2025

2024
Block-Wise Mixed-Precision Quantization: Enabling High Efficiency for Practical ReRAM-Based DNN Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2024

Neuro-Symbolic Computing: Advancements and Challenges in Hardware-Software Co-Design.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

Memory Is All You Need: An Overview of Compute-in-Memory Architectures for Accelerating Large Language Model Inference.
CoRR, 2024

Weight Update Scheme for 1T1R Memristor Array Based Equilibrium Propagation.
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024

2023
ESSENCE: Exploiting Structured Stochastic Gradient Pruning for Endurance-Aware ReRAM-Based In-Memory Training Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2023

Improving the Efficiency and Robustness of In-Memory Computing in Emerging Technologies.
PhD thesis, 2023

Biologically Plausible Learning on Neuromorphic Hardware Architectures.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

Improving the Robustness and Efficiency of PIM-Based Architecture by SW/HW Co-Design.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
Research Progress on Memristor: From Synapses to Computing Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Tolerating Noise Effects in Processing-in-Memory Systems for Neural Networks: A Hardware-Software Codesign Perspective.
Adv. Intell. Syst., 2022

Approximate Computing and the Efficient Machine Learning Expedition.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

HERO: hessian-enhanced robust optimization for unifying and improving generalization and quantization performance.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

On Building Efficient and Robust Neural Network Designs.
Proceedings of the 56th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2022, Pacific Grove, CA, USA, October 31, 2022

2021
Harnessing Optoelectronic Noises in a Photonic Generative Adversarial Network (GAN).
CoRR, 2021

Multi-Objective Optimization of ReRAM Crossbars for Robust DNN Inferencing under Stochastic Noise.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

2020
ReTransformer: ReRAM-based Processing-in-Memory Architecture for Transformer Acceleration.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020


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