Abhitosh Vais

Orcid: 0000-0002-0317-7720

According to our database1, Abhitosh Vais authored at least 6 papers between 2014 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
III-V HBTs on 300 mm Si substrates using merged nano-ridges and its application in the study of impact of defects on DC and RF performance.
Proceedings of the 52nd IEEE European Solid-State Device Research Conference, 2022

2021
A defect characterization technique for the sidewall surface of Nano-ridge and Nanowire based Logic and RF technologies.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

2018
Impact of slow and fast oxide traps on In0.53Ga0.47As device operation studied using CET maps.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

2016

2015
The relationship between border traps characterized by AC admittance and BTI in III-V MOS devices.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

2014
Determination of energy and spatial distribution of oxide border traps in In<sub>0.53</sub>Ga<sub>0.47</sub>As MOS capacitors from capacitance-voltage characteristics measured at various temperatures.
Microelectron. Reliab., 2014


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