David J. Frank

According to our database, David J. Frank authored at least 18 papers between 1995 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Low power cryogenic RF ASICs for quantum computing.

David J. Frank, Sudipto Chakraborty, Kevin Tien, Pat Rosno, Mark Yeck, Joseph A. Glick, Raphael Robertazzi, Ray Richetta, John F. Bulzacchelli, Daniel Ramirez, Dereje Yilma, Andrew Davies, Rajiv V. Joshi, Scott Lekuch, Ken Inoue, Devin Underwood, Dorothy Wisnieff, Chris Baks, John Timmerwilke, Peilin Song, Blake R. Johnson, Brian P. Gaucher, Daniel J. Friedman

Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2022

A Cryo-CMOS Low-Power Semi-Autonomous Transmon Qubit State Controller in 14-nm FinFET Technology.

Sudipto Chakraborty, David J. Frank, Kevin Tien, Pat Rosno, Mark Yeck, Joseph A. Glick, Raphael Robertazzi, Ray Richetta, John F. Bulzacchelli, Devin Underwood, Daniel Ramirez, Dereje Yilma, Andrew Davies, Rajiv V. Joshi, Shawn D. Chambers, Scott Lekuch, Ken Inoue, Dorothy Wisnieff, Christian W. Baks, Donald S. Bethune, John Timmerwilke, Thomas Fox, Peilin Song, Blake R. Johnson, Brian P. Gaucher, Daniel J. Friedman

IEEE J. Solid State Circuits, 2022

A Cryo-CMOS Low-Power Semi-Autonomous Qubit State Controller in 14nm FinFET Technology.

David J. Frank, Sudipto Chakraborty, Kevin Tien, Pat Rosno, Thomas Fox, Mark Yeck, Joseph A. Glick, Raphael Robertazzi, Ray Richetta, John F. Bulzacchelli, Daniel Ramirez, Dereje Yilma, Andrew Davies, Rajiv V. Joshi, Shawn D. Chambers, Scott Lekuch, Ken Inoue, Devin Underwood, Dorothy Wisnieff, Christian W. Baks, Donald Bethune, John Timmerwilke, Blake R. Johnson, Brian P. Gaucher, Daniel J. Friedman

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

A Cryo-CMOS Transmon Qubit Controller and Verification with FPGA Emulation.

Kevin Tien, Ken Inoue, Scott Lekuch, David J. Frank, Sudipto Chakraborty, Pat Rosno, Thomas Fox, Mark Yeck, Joseph A. Glick, Raphael Robertazzi, Ray Richetta, John F. Bulzacchelli, Daniel Ramirez, Dereje Yilma, Andrew Davies, Rajiv V. Joshi, Devin Underwood, Dorothy Wisnieff, Christian W. Baks, Donald Bethune, John Timmerwilke, Blake R. Johnson, Brian P. Gaucher, Daniel J. Friedman

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2016

Synthesis design strategies for energy-efficient microprocessors.

Ching Zhou, Yu-Shiang Lin, Pong-Fei Lu, Bruce M. Fleischer, David J. Frank, Leland Chang

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

2010

Practical Strategies for Power-Efficient Computing Technologies.

Leland Chang, David J. Frank, Robert K. Montoye, Steven J. Koester, Brian L. Ji, Paul W. Coteus, Robert H. Dennard, Wilfried Haensch

Proc. IEEE, 2010

2006

Three-dimensional integrated circuits.

Anna W. Topol, Douglas C. La Tulipe Jr., Leathen Shi, David J. Frank, Kerry Bernstein, Steven E. Steen, Arvind Kumar, Gilbert U. Singco, Albert M. Young, Kathryn W. Guarini, Mei-Kei Ieong

IBM J. Res. Dev., 2006

Optimizing CMOS technology for maximum performance.

David J. Frank, Wilfried Haensch, Ghavam G. Shahidi, Omer H. Dokumaci

IBM J. Res. Dev., 2006

High-performance CMOS variability in the 65-nm regime and beyond.

Kerry Bernstein, David J. Frank, Anne E. Gattiker, Wilfried Haensch, Brian L. Ji, Sani R. Nassif, Edward J. Nowak, Dale J. Pearson, Norman J. Rohrer

IBM J. Res. Dev., 2006

Design and CAD challenges in 45nm CMOS and beyond.

David J. Frank, Ruchir Puri, Dorel Toma

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

2002

Power-constrained CMOS scaling limits.

David J. Frank

IBM J. Res. Dev., 2002

2001

Device scaling limits of Si MOSFETs and their application dependencies.

David J. Frank, Robert H. Dennard, Edward J. Nowak, Paul M. Solomon, Yuan Taur, Hon-Sum Philip Wong

Proc. IEEE, 2001

1999

Nanoscale CMOS.

Hon-Sum Philip Wong, David J. Frank, Paul M. Solomon, Clement H. J. Wann, Jefferey J. Welser

Proc. IEEE, 1999

1997

CMOS scaling into the nanometer regime.

Yuan Taur, Douglas A. Buchanan, Wei Chen, David J. Frank, Khalid E. Ismail, Shih-Hsien Lo, George A. Sai-Halasz, Raman G. Viswanathan, Hsing-Jen C. Wann, Shalom J. Wind, Hon-Sum Philip Wong

Proc. IEEE, 1997

Supply and threshold voltage optimization for low power design.

David J. Frank, Paul M. Solomon, Scott K. Reynolds, John Shin

Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

1996

Comparison of high speed voltage-scaled conventional and adiabatic circuits.

David J. Frank

Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

1995

CMOS scaling into the 21st century: 0.1 µm and beyond.

Yuan Taur, Yuh-Jier Mii, David J. Frank, H.-S. Philip Wong, Douglas A. Buchanan, Shalom J. Wind, Stephen A. Rishton, Watson A. Sai-Halasz, Edward J. Nowak

IBM J. Res. Dev., 1995

Electroid-oriented adiabatic switching circuits.

David J. Frank, Paul M. Solomon

Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995