Zhenyu Wang

According to our database, Zhenyu Wang authored at least 6 papers between 2022 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

HISIM: Analytical Performance Modeling and Design Space Exploration of 2.5D/3D Integration for AI Computing.

Zhenyu Wang, Pragnya Sudershan Nalla, Jingbo Sun, A. Alper Goksoy, Sumit K. Mandal, Jae-Sun Seo, Vidya A. Chhabria, Jeff Zhang, Chaitali Chakrabarti, Ümit Y. Ogras, Yu Cao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., August, 2025

2024

SHIFFT: A Scalable Hybrid In-Memory Computing FFT Accelerator.

Pragnya Sudershan Nalla, Zhenyu Wang, Sapan Agarwal, T. Patrick Xiao, Christopher H. Bennett, Matthew J. Marinella, Jae-sun Seo, Yu Cao

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

Exploiting 2.5D/3D Heterogeneous Integration for AI Computing.

Zhenyu Wang, Jingbo Sun, A. Alper Goksoy, Sumit K. Mandal, Yaotian Liu, Jae-Sun Seo, Chaitali Chakrabarti, Ümit Y. Ogras, Vidya A. Chhabria, Jeff Zhang, Yu Cao

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023

Benchmarking Heterogeneous Integration with 2.5D/3D Interconnect Modeling.

Zhenyu Wang, Jingbo Sun, A. Alper Goksoy, Sumit K. Mandal, Jae-Sun Seo, Chaitali Chakrabarti, Ümit Y. Ogras, Vidya A. Chhabria, Yu Cao

Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022

Hybrid RRAM/SRAM in-Memory Computing for Robust DNN Acceleration.

Gokul Krishnan, Zhenyu Wang, Injune Yeo, Li Yang, Jian Meng, Maximilian Liehr, Rajiv V. Joshi, Nathaniel C. Cady, Deliang Fan, Jae-Sun Seo, Yu Cao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Big-Little Chiplets for In-Memory Acceleration of DNNs: A Scalable Heterogeneous Architecture.

Gokul Krishnan, A. Alper Goksoy, Sumit K. Mandal, Zhenyu Wang, Chaitali Chakrabarti, Jae-sun Seo, Ümit Y. Ogras, Yu Cao

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022