Zhidao Zhou

According to our database1, Zhidao Zhou authored at least 15 papers between 2023 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
A hybrid-tiling attention accelerator with a fully-pipelined balanced systolic array in 3D hybrid-bonding near-DRAM integration.
Microelectron. J., 2026

A 12nm 4Mb 104.56-to-137.75TFLOPS/W Charge-Trap Transistor-Based Computing-in-Memory Macro Using Analog-Predict-Digital-Compute for AI Edge Devices.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026

30.6 A 16Mb 166.8TOPS/W Near-Memory Phase-Domain-Computing Ferroelectric NAND Flash for Approximate Nearest Neighbor Search on Edge Devices.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026

A BEOL Ferroelectric FET-based Computing Unit for Digital Computing-in-Memory.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

2025
An RRAM Digital Computing-in-Memory Macro With Dual-Mode Multiplication and Maximum Value Rounding Adder Tree.
IEEE Trans. Very Large Scale Integr. Syst., June, 2025

An energy-efficient FeFET-based computing-in-memory macro using BEOL-integrated HZO ferroelectric capacitors.
Sci. China Inf. Sci., 2025

2024
Write-Verify-Free MLC RRAM Using Nonbinary Encoding for AI Weight Storage at the Edge.
IEEE Trans. Very Large Scale Integr. Syst., February, 2024

Multi-stage Attention Network with Auxiliary Information Refinement for VVC In-loop Filtering.
Proceedings of the IEEE International Conference on Visual Communications and Image Processing, 2024

PFT-ILF: In-loop Filter with Partition Feature Transform for Versatile Video Coding.
Proceedings of the IEEE International Conference on Visual Communications and Image Processing, 2024

34.9 A Flash-SRAM-ADC-Fused Plastic Computing-in-Memory Macro for Learning in Neural Networks in a Standard 14nm FinFET Process.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

A 2T P-Channel Logic Flash Cell for Reconfigurable Interconnection in Chiplet-Based Computing-In-Memory Accelerators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

PFR-VC: Learning-Based Video Compression Framework with Predicted Frame Refinement.
Proceedings of the International Joint Conference on Neural Networks, 2024

Cross-Frame Integrated Prediction for Feature-Space Video Compression.
Proceedings of the International Joint Conference on Neural Networks, 2024

LIghtweight Texture-Guided Fast Partition Method for Luma and Chroma Intra Coding in VVC.
Proceedings of the IEEE International Conference on Multimedia and Expo, 2024

2023
A 28-nm RRAM Computing-in-Memory Macro Using Weighted Hybrid 2T1R Cell Array and Reference Subtracting Sense Amplifier for AI Edge Inference.
IEEE J. Solid State Circuits, October, 2023


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