Weizeng Li

According to our database, Weizeng Li authored at least 11 papers between 2022 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2026

A hybrid-tiling attention accelerator with a fully-pipelined balanced systolic array in 3D hybrid-bonding near-DRAM integration.

Zhongze Han, Hanghang Gao, Weizeng Li, Zhi Li, Zhidao Zhou, Yiman Wang, Junzhe Shen, Junyu Zhu, Bohan Wang, Jianguo Yang, Jinshan Yue, Hongyang Hu, Chunmeng Dou

Microelectron. J., 2026

A 12nm 4Mb 104.56-to-137.75TFLOPS/W Charge-Trap Transistor-Based Computing-in-Memory Macro Using Analog-Predict-Digital-Compute for AI Edge Devices.

Junzhe Shen, Zhidao Zhou, Wenfeng Zha, Zhi Li, Weizeng Li, Bohan Wang, Junyu Zhu, Hanghang Gao, Zhongze Han, Yiman Wang, Linfang Wang, Hongyang Hu, Qing Luo, Chunmeng Dou, Ming Liu

Proceedings of the IEEE International Solid-State Circuits Conference, 2026

30.6 A 16Mb 166.8TOPS/W Near-Memory Phase-Domain-Computing Ferroelectric NAND Flash for Approximate Nearest Neighbor Search on Edge Devices.

Weizeng Li, Bohan Wang, Zhidao Zhou, Junyu Zhu, Zhi Li, Junzhe Shen, Wenfeng Zha, Zhongze Han, Yiman Wang, Linfang Wang, Hongyang Hu, Qing Luo, Chunmeng Dou, Ming Liu

Proceedings of the IEEE International Solid-State Circuits Conference, 2026

2025

An RRAM Digital Computing-in-Memory Macro With Dual-Mode Multiplication and Maximum Value Rounding Adder Tree.

Wang Ye, Hanghang Gao, Zhidao Zhou, Linfang Wang, Weizeng Li, Zhi Li, Jinshan Yue, Xiaoxin Xu, Jianguo Yang, Hongyang Hu, Chunmeng Dou

IEEE Trans. Very Large Scale Integr. Syst., June, 2025

An energy-efficient FeFET-based computing-in-memory macro using BEOL-integrated HZO ferroelectric capacitors.

Weizeng Li, Zhidao Zhou, Linfang Wang, Junyu Zhu, Junzhe Shen, Hongyang Hu, Baihan Wang, Zhi Li, Wang Ye, Zhongze Han, Hanghang Gao, Chunmeng Dou

Sci. China Inf. Sci., 2025

2024

Write-Verify-Free MLC RRAM Using Nonbinary Encoding for AI Weight Storage at the Edge.

Junjie An, Zhidao Zhou, Linfang Wang, Wang Ye, Weizeng Li, Hanghang Gao, Zhi Li, Jinghui Tian, Yan Wang, Hongyang Hu, Jinshan Yue, Lingyan Fan, Shibing Long, Qi Liu, Chunmeng Dou

IEEE Trans. Very Large Scale Integr. Syst., February, 2024

First Demonstration of Monolithic Three-Dimensional Integration of Ultra-High Density Hybrid IGZO/Si SRAM and IGZO 2T0C DRAM Achieving Record-Low Latency (5000s).

Menggan Liu, Zhi Li, Wendong Lu, Kaifei Chen, Jiebin Niu, Fuxi Liao, Zijing Wu, Congyan Lu, Weizeng Li, Di Geng, Nianduan Lu, Chunmeng Dou, Guanhua Yang, Ling Li, Ming Liu

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

34.9 A Flash-SRAM-ADC-Fused Plastic Computing-in-Memory Macro for Learning in Neural Networks in a Standard 14nm FinFET Process.

Linfang Wang, Weizeng Li, Zhidao Zhou, Hanghang Gao, Zhi Li, Wang Ye, Hongyang Hu, Jing Liu, Jinshan Yue, Jianguo Yang, Qing Luo, Chunmeng Dou, Qi Liu, Ming Liu

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

A 2T P-Channel Logic Flash Cell for Reconfigurable Interconnection in Chiplet-Based Computing-In-Memory Accelerators.

Weizeng Li, Linfang Wang, Zhi Li, Wang Ye, Zhidao Zhou, Haiyang Zhou, Hanghang Gao, Jinshan Yue, Hongyang Hu, Fengman Liu, Qing Luo, Chunmeng Dou

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023

A 28-nm RRAM Computing-in-Memory Macro Using Weighted Hybrid 2T1R Cell Array and Reference Subtracting Sense Amplifier for AI Edge Inference.

Wang Ye, Linfang Wang, Zhidao Zhou, Junjie An, Weizeng Li, Hanghang Gao, Zhi Li, Jinshan Yue, Hongyang Hu, Xiaoxin Xu, Jianguo Yang, Jing Liu, Dashan Shang, Feng Zhang, Jinghui Tian, Chunmeng Dou, Qi Liu, Ming Liu

IEEE J. Solid State Circuits, October, 2023

2022

RRAM Computing-in-Memory Using Transient Charge Transferring for Low-Power and Small-Latency AI Edge Inference.

Linfang Wang, Junjie An, Wang Ye, Weizeng Li, Hanghang Gao, Yangu He, Jianfeng Gao, Jinshan Yue, Lingyan Fan, Chunmeng Dou

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022