Scott Hauck

According to our database1, Scott Hauck authored at least 94 papers between 1992 and 2020.

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Awards

IEEE Fellow

IEEE Fellow 2016, "For contributions to Field-Programmable Gate Array based systems".

Timeline

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PhD thesis 
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Bibliography

2020
GPU coprocessors as a service for deep learning inference in high energy physics.
CoRR, 2020

FPGAs-as-a-Service Toolkit (FaaST).
Proceedings of the 2020 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing, 2020

2018
FPGA Acceleration of Short Read Alignment.
CoRR, 2018

2017
K-Mer Counting Using Bloom Filters with an FPGA-Attached HMC.
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

2015
A Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services.
IEEE Micro, 2015

Offset Pipelined Scheduling: Conditional Branching for CGRAs.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

A Scalable High-Bandwidth Architecture for Lossless Compression on FPGAs.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

2014
A Scalable Multi-engine Xpress9 Compressor with Asynchronous Data Transfer.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

2013
Accelerating ncRNA homology search with FPGAs.
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

2012
Multi-kernel floorplanning for enhanced CGRAS.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Adding dataflow-driven execution control to a Coarse-Grained Reconfigurable Array.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Dataflow-driven execution control in a coarse-grained reconfigurable array (abstract only).
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

Hardware Acceleration of Short Read Mapping.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

2011
Performance of partial reconfiguration in FPGA systems: A survey and a cost model.
ACM Trans. Reconfigurable Technol. Syst., 2011

Energy-efficient specialization of functional units in a coarse-grained reconfigurable array.
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

Dynamic Communication in a Coarse Grained Reconfigurable Array.
Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

Accelerating Statistical LOR Estimation for a High-Resolution PET Scanner Using FPGA Devices and a High Level Synthesis Tool.
Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

2010
Reconfigurable Computing Systems.
Proceedings of the Encyclopedia of Software Engineering, 2010

The Future of Integrated Circuits: A Survey of Nanoelectronics.
Proc. IEEE, 2010

Software Managed Distributed Memories in MPPAs.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Managing Short-Lived and Long-Lived Values in Coarse-Grained Reconfigurable Arrays.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Impulse C vs. VHDL for Accelerating Tomographic Reconstruction.
Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010

2009
Static versus scheduled interconnect in Coarse-Grained Reconfigurable Arrays.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

FPGA-based front-end electronics for positron emission tomography.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

SPR: an architecture-adaptive CGRA mapping tool.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

2008
Automatic Design of Reconfigurable Domain-Specific Flexible Cores.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Architectural Modifications to Enhance the Floating-Point Performance of FPGAs.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Fpga-based data acquisition system for a positron emission tomography (PET) scanner.
Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

Simultaneous Retiming and Placement for Pipelined Netlists.
Proceedings of the 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, 2008

Enhancing timing-driven FPGA placement for pipelined netlists.
Proceedings of the 45th Design Automation Conference, 2008

2007
Automatic Creation of Domain-Specific Reconfigurable CPLDs for SoC.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Automatic Design of Area-Efficient Configurable ASIC Cores.
IEEE Trans. Computers, 2007

Active Learning Techniques in a CAD Course.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007

2006
PipeRoute: a pipelining-aware router for reconfigurable architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Field-Programmable Gate Arrays in Embedded Systems.
EURASIP J. Embed. Syst., 2006

Architectural Modifications to Improve Floating-Point Unit Efficiency in FPGAs.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Improving performance and robustness of domain-specific CPLDs.
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

Armada: timing-driven pipeline-aware routing for FPGAs.
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

Embedded floating-point units in FPGAs.
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

Predictive Coding of Hyperspectral Images.
Proceedings of the Hyperspectral Data Compression, 2006

2005
SPIHT image compression on FPGAs.
IEEE Trans. Circuits Syst. Video Technol., 2005

Resource allocation for coarse-grain FPGA development.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Précis: A Usercentric Word-Length Optimization Tool.
IEEE Des. Test Comput., 2005

Accelerating FPGA Routing Using Architecture-Adaptive A* Techniques.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

Architecture-Adaptive Routability-Driven Placement for FPGAs.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Architecture Adaptive Routability-Driven Placement for FPGAs (abstract only).
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

Automating the Layout of Reconfigurable Subsystems Using Circuit Generators.
Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005

A Comparison of Floating Point and Logarithmic Number Systems for FPGAs.
Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005

Architecture-adaptive range limit windowing for simulated annealing FPGA placement.
Proceedings of the 42nd Design Automation Conference, 2005

2004
The Chimaera reconfigurable functional unit.
IEEE Trans. Very Large Scale Integr. Syst., 2004

Automating the Layout of Reconfigurable Subsystems via Template Reduction.
Proceedings of the Field Programmable Logic and Application, 2004

Automatic Creation of Reconfigurable PALs/PLAs for SoC.
Proceedings of the Field Programmable Logic and Application, 2004

Exploration of pipelined FPGA interconnect structures.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

Flexibility measurement of domain-specific reconfigurable hardware.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

Least-significant bit optimization techniques for FPGAs.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

Automated Least-Significant Bit Datapath Optimization for FPGAs.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

Reduced Complexity Wavelet-Based Predictive Coding of Hyperspectral Images for FPGA Implementation.
Proceedings of the 2004 Data Compression Conference (DCC 2004), 2004

2003
Harnessing FPGAs for Computer Architecture Education.
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

APHYDS: The Academic Physical Design Skeleton.
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

PipeRoute: a pipelining-aware router for FPGAs.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

Track placement: orchestrating routing structures to maximize routability.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

Issues and Approaches to Coarse-Grain Reconfigurable Architecture Development.
Proceedings of the 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 2003

2002
Configuration relocation and defragmentation for run-time reconfigurable computing.
IEEE Trans. Very Large Scale Integr. Syst., 2002

Reconfigurable computing: a survey of systems and software.
ACM Comput. Surv., 2002

Flexible Routing Architecture Generation for Domain-Specific Reconfigurable Subsystems.
Proceedings of the Field-Programmable Logic and Applications, 2002

Automatic layout of domain-specific reconfigurable subsystems for system-on-a-chip.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2002

Configuration prefetching techniques for partial reconfigurable coprocessor with relocation and defragmentation.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2002

Hyperspectral Image Compression on Reconfigurable Platforms.
Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

Précis: A Design-Time Precision Analysis Tool.
Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

2001
Runtime and quality tradeoffs in FPGA placement and routing.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2001

Is marriage in the cards for programmable logic, microprocessors and ASICs?
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2001

Configuration Compression for Virtex FPGAs.
Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001

Totem: Custom Reconfigurable Array Generation.
Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001

2000
High-performance carry chains for FPGA's.
IEEE Trans. Very Large Scale Integr. Syst., 2000

CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit.
Proceedings of the 27th International Symposium on Computer Architecture (ISCA 2000), 2000

Configuration Caching Management Techniques for Reconfigurable Computing.
Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

Configuration Relocation and Defragmentation for Reconfigurable Computing.
Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

A MATLAB Compiler for Distributed, Heterogeneous, Reconfigurable Computing Systems.
Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

1999
Configuration compression for the Xilinx XC6200 FPGA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Evaluation and optimization of replication algorithms for logic bipartitioning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Don't Care Discovery for FPGA Configuration Compression.
Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999

Runlength Compression Techniques for FPGA Configurations.
Proceedings of the 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 1999

1998
Mesh routing topologies for multi-FPGA systems.
IEEE Trans. Very Large Scale Integr. Syst., 1998

High-Performance Carry Chains for FPGAs.
Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

Configuration Prefetch for Single Context Reconfigurable Coprocessors.
Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

Data Security for Web-based CAD.
Proceedings of the 35th Conference on Design Automation, 1998

1997
Pin assignment for multi-FPGA systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

An evaluation of bipartitioning techniques.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Replication for logic bipartitioning.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

1995
Placement and routing tools for the Triptych FPGA.
IEEE Trans. Very Large Scale Integr. Syst., 1995

The Triptych FPGA architecture.
IEEE Trans. Very Large Scale Integr. Syst., 1995

Logic Partition Orderings for Multi-FPGA Systems.
Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays, 1995

1994
An FPGA for Implementing Asynchronous Circuits.
IEEE Des. Test Comput., 1994

1992
MONTAGNE: An FPL for Synchronous and Asynchronous Circuits.
Proceedings of the Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping, Second International Workshop on Field-Programmable Logic and Applications, Vienna, Austria, August 31, 1992


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