Vlad Mihai Sima
According to our database1, Vlad Mihai Sima authored at least 28 papers between 2007 and 2018.
Legend:Book In proceedings Article PhD thesis Other
Hardware acceleration of BWA-MEM genomic short read mapping for longer read lengths.
Comput. Biology Chem., 2018
Comparative Analysis of System-Level Acceleration Techniques in Bioinformatics: A Case Study of Accelerating the Smith-Waterman Algorithm for BWA-MEM.
Proceedings of the 18th IEEE International Conference on Bioinformatics and Bioengineering, 2018
High Performance Streaming Smith-Waterman Implementation with Implicit Synchronization on Intel FPGA using OpenCL.
Proceedings of the 17th IEEE International Conference on Bioinformatics and Bioengineering, 2017
A Survey and Evaluation of FPGA High-Level Synthesis Tools.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016
An Efficient GPUAccelerated Implementation of Genomic Short Read Mapping with BWAMEM.
SIGARCH Computer Architecture News, 2016
Power-efficiency analysis of accelerated BWA-MEM implementations on heterogeneous computing platforms.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016
Power-Efficient Accelerated Genomic Short Read Mapping on Heterogeneous Computing Platforms.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016
GPU-Accelerated BWA-MEM Genomic Mapping Algorithm Using Adaptive Load Balancing.
Proceedings of the Architecture of Computing Systems - ARCS 2016, 2016
An FPGA-based systolic array to accelerate the BWA-MEM genomic mapping algorithm.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015
Heterogeneous Hardware/Software Acceleration of the BWA-MEM DNA Alignment Algorithm.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
FPGA acceleration of the pair-HMMs forward algorithm for DNA sequence analysis.
Proceedings of the 2015 IEEE International Conference on Bioinformatics and Biomedicine, 2015
FPGA-accelerated Monte-Carlo integration using stratified sampling and Brownian bridges.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014
High-Level Synthesis in the Delft Workbench Hardware/Software Co-design Tool-Chain.
Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014
DRuiD: Designing reconfigurable architectures with decision-making support.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
Quipu: A Statistical Model for Predicting Hardware Resources.
Run-time optimization of a dynamically reconfigurable embedded system through performance prediction.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013
Compiler Assisted Runtime Adaptation.
PhD thesis, 2012
A lightweight speculative and predicative scheme for hardware execution.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012
Area constraint propagation in high level synthesis.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012
DWARV 2.0: A CoSy-based C-to-VHDL hardware compiler.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012
Using multi-objective design space exploration to enable run-time resource management for reconfigurable architectures.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
IP-XACT extensions for Reconfigurable Computing.
Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011
HArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms.
IEEE Micro, 2010
Runtime Memory Allocation in a Heterogeneous Reconfigurable Platform.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009
Runtime decision of hardware or software execution on a heterogeneous reconfigurable platform.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009
Compiler assisted runtime task scheduling on a reconfigurable computer.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009
Resource allocation algorithm and OpenMP extensions for parallel execution on a heterogeneous reconfigurable platform.
Proceedings of the FPL 2008, 2008
HARTES Toolchain Early Evaluation: Profiling, Compilation and HDL Generation.
Proceedings of the FPL 2007, 2007