Razvan Nane

According to our database1, Razvan Nane authored at least 23 papers between 2011 and 2022.

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In proceedings 
PhD thesis 


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On csauthors.net:


Hardware Acceleration of High-Performance Computational Flow Dynamics Using High-Bandwidth Memory-Enabled Field-Programmable Gate Arrays.
ACM Trans. Reconfigurable Technol. Syst., 2022

OpenQL: A Portable Quantum Programming Framework for Quantum Accelerators.
ACM J. Emerg. Technol. Comput. Syst., 2022

SDC-based Resource Constrained Scheduling for Quantum Control Architectures.
CoRR, 2022

Hardware Acceleration of HPC Computational Flow Dynamics using HBM-enabled FPGAs.
CoRR, 2021

Skeleton-Based Synthesis Flow for Computation-in-Memory Architectures.
IEEE Trans. Emerg. Top. Comput., 2020

Sparstition: A Partitioning Scheme for Large-Scale Sparse Matrix Vector Multiplication on FPGA.
Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

On the Implementation of Computation-in-Memory Parallel Adder.
IEEE Trans. Very Large Scale Integr. Syst., 2017

A Domain-Specific Language and Compiler for Computation-in-Memory Skeletons.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

A Survey and Evaluation of FPGA High-Level Synthesis Tools.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

An Image Processing VLIW Architecture for Real-Time Depth Detection.
Proceedings of the 28th International Symposium on Computer Architecture and High Performance Computing, 2016

Skeleton-based design and simulation flow for Computation-in-Memory architectures.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Parallel matrix multiplication on memristor-based computation-in-memory architecture.
Proceedings of the International Conference on High Performance Computing & Simulation, 2016

Computation-in-memory based parallel adder.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

Low-Cost Software Control-Flow Error Recovery.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Automatic Hardware Generation for Reconfigurable Architectures.
PhD thesis, 2014

High-Level Synthesis in the Delft Workbench Hardware/Software Co-design Tool-Chain.
Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014

Quipu: A Statistical Model for Predicting Hardware Resources.
ACM Trans. Reconfigurable Technol. Syst., 2013

Controlling a complete hardware synthesis toolchain with LARA aspects.
Microprocess. Microsystems, 2013

Deriving Resource Efficient Designs Using the REFLECT Aspect-Oriented Approach - (Extended Abstract).
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013

A lightweight speculative and predicative scheme for hardware execution.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Area constraint propagation in high level synthesis.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

DWARV 2.0: A CoSy-based C-to-VHDL hardware compiler.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

IP-XACT extensions for Reconfigurable Computing.
Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011