Changze Liu
According to our database1,
Changze Liu
authored at least 9 papers
between 2011 and 2022.
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Bibliography
2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
2021
Performance Trade-Off Scenarios for GAA Nanosheet FETs Considering Inner-spacers and Epi-induced Stress: Understanding & Mitigating Process Risks.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021
Analog IC Aging-induced Degradation Estimation via Heterogeneous Graph Convolutional Networks.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2018
Investigation on NBTI-induced dynamic variability in nanoscale CMOS devices: Modeling, experimental evidence, and impact on circuits.
Microelectron. Reliab., 2018
New insights into the HCI degradation of pass-gate transistor in advanced FinFET technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2018
2015
Systematical study of 14nm FinFET reliability: From device level stress to product HTOL.
Proceedings of the IEEE International Reliability Physics Symposium, 2015
2012
Self-heating effects in gate-all-around silicon nanowire MOSFETs: Modeling and analysis.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
2011
Microelectron. Reliab., 2011
Characterization and analysis of gate-all-around Si nanowire transistors for extreme scaling.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011