Sangwoo Pae

According to our database1, Sangwoo Pae authored at least 35 papers between 2006 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2025
Novel Linear Model for OFF-State Stress Causing Stand-By Current of Advanced VNAND Chip.
Proceedings of the IEEE International Reliability Physics Symposium, 2025

Reliability Characterization Using Accelerated Methods of 1Tb 9th-Gen VNAND for TLC/QLC applications.
Proceedings of the IEEE International Reliability Physics Symposium, 2025

2024
Comprehensive Study of SER in FDSOI-Planar: 28 nm to 18 nm Scaling Effect and Temperature Dependence.
Proceedings of the IEEE International Reliability Physics Symposium, 2024

Soft-Error Sensitivity in SRAM Manufactured by Bulk Gate-All-Around (GAA) Technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2024

V-Ramp VBD Prediction Method Using OCD-Spectrum and Deep-Learning, and Application to Early Detection of V-NAND Low Metal Reliability Risk.
Proceedings of the IEEE International Reliability Physics Symposium, 2024

Effect of Off-State Stress on Data-Valid Window Margin for Advanced DRAM Using HK/MG Process Technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2024

Virtual FA Methodology for DRAM: Real-Time Analysis and Risk Assessment Method Using Telemetry.
Proceedings of the IEEE International Reliability Physics Symposium, 2024

2023
Customized wafer level verification methodology: quality risk pre-diagnosis with enhanced screen-ability of stand-by stress-related deteriorations.
Proceedings of the IEEE International Reliability Physics Symposium, 2023

Impact of Design and Process on Alpha-Induced SER in 4 nm Bulk-FinFET SRAM.
Proceedings of the IEEE International Reliability Physics Symposium, 2023

2021
Effect of High Temperature on Recovery of Hot Carrier Degradation of scaled nMOSFETs in DRAM.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

The Characterization of Degradation on various SiON pMOSFET transistors under AC/DC NBTI stress.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

2020
Investigating of SER in 28 nm FDSOI-Planar and Comparing with SER in Bulk-FinFET.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Backside Alpha-Irradiation Test in Flip-Chip Package in EUV 7 nm FinFET SRAM.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Early Diagnosis and Prediction of Wafer Quality Using Machine Learning on sub-10nm Logic Technology.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Advanced Self-heating Model and Methodology for Layout Proximity Effect in FinFET Technology.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020


Reliability on EUV Interconnect Technology for 7nm and beyond.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

2019
SEIFF: Soft Error Immune Flip-Flop for Mitigating Single Event Upset and Single Event Transient in 10 nm FinFET.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Aging-Aware Design Verification Methods Under Real Product Operating Conditions.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Localized Layout Effect Related Reliability Approach in 8nm FinFETs Technology: From Transistor to Circuit.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Reliability of 8Mbit Embedded-STT-MRAM in 28nm FDSOI Technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

2018
Investigation of BTI characteristics and its behavior on 10 nm SRAM with high-k/metal gate FinFET technology having multi-V<sub>T</sub> gate stack.
Microelectron. Reliab., 2018

Investigation of alpha-induced single event transient (SET) in 10 nm FinFET logic circuit.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

Effects of Far-BEOL anneal on the WLR and product reliability characterization of FinFET process technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

A systematic study of gate dielectric TDDB in FinFET technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

Reliability characterization of advanced CMOS image sensor (CIS) with 3D stack and in-pixel DTI.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

Optimal design of dummy ball array in wafer level package to improve board level thermal cycle reliability (BLR).
Proceedings of the IEEE International Reliability Physics Symposium, 2018

2015
Reliability of fine pitch COF: Influence of surface morphology and CuSn intermetallic compound formation.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Effects of front-end-of line process variations and defects on retention failure of flash memory: Charge loss/gain mechanism.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Contact resistance of solder bump with low cost photosensitive polyimide for high performance SoC.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Systematical study of 14nm FinFET reliability: From device level stress to product HTOL.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Radiation-induced soft error rate analyses for 14 nm FinFET SRAM devices.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

CPI reliability and EMI benefit for MIM CAP embedded C4 package.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

SRAM stability design comprehending 14nm FinFET reliability.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

2006
PMOS NBTI-induced circuit mismatch in advanced technologies.
Microelectron. Reliab., 2006


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