Hung-Hsi Hsu

Orcid: 0009-0007-3511-5333

According to our database1, Hung-Hsi Hsu authored at least 5 papers between 2023 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
A Nonvolatile AI-Edge Processor With SLC-MLC Hybrid ReRAM Compute-in-Memory Macro Using Current-Voltage-Hybrid Readout Scheme.
IEEE J. Solid State Circuits, January, 2024

34.8 A 22nm 16Mb Floating-Point ReRAM Compute-in-Memory Macro with 31.2TFLOPS/W for AI Edge Devices.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023
A 28nm Nonvolatile AI Edge Processor using 4Mb Analog-Based Near-Memory-Compute ReRAM with 27.2 TOPS/W for Tiny AI Edge Devices.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Challenges in Circuits of Nonvolatile Compute-In-Memory for Edge AI Chips.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

A Nonvolatile Al-Edge Processor with 4MB SLC-MLC Hybrid-Mode ReRAM Compute-in-Memory Macro and 51.4-251TOPS/W.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023


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